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US 2020/0350221 A1Published application
Interposer Test Structures and Methods
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
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Abstract
An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.
Claims20
A semiconductor device comprising:
- an integrated circuit die, the integrated circuit die comprising a plurality of die contact pads and a plurality of die interconnects, each of the plurality of die interconnects electrically coupling two of the plurality of die contact pads to each other;
- and
- an interposer bonded to the integrated circuit die, the interposer comprising a plurality of interposer contact pads, a plurality of interposer interconnects, a first test connection, and a second test connection, wherein:
- each of the plurality of interposer interconnects electrically couple two of the plurality of interposer contact pads to each other;
- each of the plurality of interposer contact pads are coupled to corresponding ones of the plurality of die contact pads;
- and
- the plurality of interposer interconnects, the plurality of interposer contact pads, the plurality of die contact pads, and the plurality of die interconnects form a daisy chain electrically interposed between the first test connection and the second test connection.
4 more elements
A semiconductor device comprising:
- an interposer, the interposer comprising a first interposer sense pad, a second interposer sense pad, and a first interposer under test pad, the interposer further comprising a first probe pad electrically coupled to the first interposer sense pad, a second probe pad electrically coupled to the second interposer sense pad, and at least one third probe pad electrically coupled to the first interposer under test pad;
- and
- a die bonded to the interposer, the die having a first die sense bond pad, a second die sense bond pad, and a first die under test bond pad, the first die sense bond pad being coupled to the first interposer sense pad by a first bump, the second die sense bond pad being coupled to the second interposer sense pad by a second bump, the first die under test bond pad being coupled to the first interposer under test pad, wherein the first die sense bond pad is electrically coupled to the first die under test bond pad through one or more metallization layers on the die and wherein the second die sense bond pad is electrically coupled to the first die under test bond pad through the one or more metallization layers on the die, wherein the first probe pad, the second probe pad, and the at least one third probe pad are not covered by the die in a plan view.
A semiconductor device comprising:
- an integrated circuit die, the integrated circuit die have a first die contact pad and a second die contact pad, the first die contact pad being electrically coupled to the second die contact pad;
- and
- an interposer, the interposer having a first interposer contact pad and a second interposer contact pad, the first interposer contact pad being coupled to the first die contact pad, the second interposer contact pad being coupled to the second die contact pad, the interposer having a first test connection and a second test connection, the first test connection being electrically coupled to the first interposer contact pad, the second test connection being electrically coupled to the second interposer contact pad.
Dependencies are inferred from the claim text.