# US 2020/0350185 A1 · Semiconductor fabrication with electrochemical apparatus

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- Number: US 2020/0350185 A1
- Document ID: US20200350185A1
- Status: Published application
- Kind: A1
- Application number: 16/933,727
- Filed: 2020-07-20
- Published: 2020-11-05
- Earliest claimed: 2017-09-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Andrew Joseph KELLY; Yusuke ONIKI
- Web page: https://patentgrep.com/patent/US20200350185A1

## CPC

- H10P 72/0426: {with the semiconductor substrates being dipped in baths or vessels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- C25D 17/00: Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25F 3/12: of semiconducting materials
- C25F 7/00: Constructional parts, or assemblies thereof, of cells for electrolytic removal of material from objects (for both electrolytic coating and removal C25D); Servicing or operating
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/503: {having non-rectangular cross-sections}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/01332: {Making the insulator}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10P 14/6306: {of the semiconductor materials}
- H10P 14/6324: {Formation by anodic treatments, e.g. anodic oxidation}
- H10P 50/613: {of Group IV materials}
- H10P 50/617: {of Group III-V materials}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/685: {being perpendicular to the channel plane}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/6309: {of silicon in uncombined form, i.e. pure silicon}
- H10P 14/6312: {of Group III-V semiconductors}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- C25D: PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25F: PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately; patterning the first and second semiconductor layers to form a fin structure; supplying a first bias to the substrate after patterning the first and second semiconductor layers; and etching the second semiconductor layers when the semiconductor substrate is supplied with the first bias, wherein etching the second semiconductor layers is performed such that the first semiconductor layers are suspended above the substrate.

## Claims

### Claim 1

A method, comprising:
depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately;
patterning the first and second semiconductor layers to form a fin structure;
supplying a first bias to the substrate after patterning the first and second semiconductor layers; and
etching the second semiconductor layers when the substrate is supplied with the first bias, wherein etching the second semiconductor layers is performed such that the first semiconductor layers are suspended above the substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein etching the second semiconductor layers comprises:
immersing the substrate in an electrolyte bath, wherein the electrolyte bath comprises a semiconductor material the same as that of the first semiconductor layers.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first bias is smaller than an oxidation potential of planes <110> and <100> of the first semiconductor layers.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first bias is larger than an oxidation potential of planes <110> and <100> of the first semiconductor layers and smaller than an oxidation potential of a plane <111> of the first semiconductor layers.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first bias is larger than an oxidation potential of a plane <111> of the first semiconductor layers.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
removing a surface oxide on one of the first semiconductor layers and the second semiconductor layers during depositing the first semiconductor layers and the second semiconductor layers over the substrate, wherein removing the surface oxide comprises:
immersing the substrate in an electrolyte bath; and
supplying a second bias to the substrate, wherein the second bias is negative.

### Claim 7

A method, comprising:
forming a gate trench between two gate spacers over a semiconductor substrate, such that the gate trench exposes a portion of the semiconductor substrate;
forming an interfacial layer in the gate trench between the gate spacers by supplying a positive bias to the semiconductor substrate to oxidize the exposed portion of the semiconductor substrate; and
forming a gate structure over the interfacial layer to fill the gate trench.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
forming an interlayer dielectric layer around the gate spacers; and
forming a mask layer over the interlayer dielectric layer, wherein forming the interfacial layer is performed when the interlayer dielectric layer is covered by the mask layer.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
removing the mask layer from the interlayer dielectric layer after forming the interfacial layer and prior to forming the gate structure.

### Claim 10 (depends on 7)

The method of claim 7, further comprising:
immersing the semiconductor substrate in an electrolyte bath prior to forming the interfacial layer.

### Claim 11 (depends on 7)

The method of claim 7, wherein the positive bias is larger than 0V and equal to or smaller than 5V.

### Claim 12

A method, comprising:
forming a source/drain region over a semiconductor substrate;
depositing a metal layer over the source/drain region;
annealing the semiconductor substrate to form a metal silicide layer by reacting the source/drain region with a portion of the metal layer;
converting an unreacted portion of the metal layer into a metal oxide layer after annealing the semiconductor substrate by supplying a positive bias to the semiconductor substrate; and
removing the metal oxide layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein depositing the metal layer over the source/drain region is performed such that the metal layer is over a top surface of an isolation structure.

### Claim 14 (depends on 13)

The method of claim 13, wherein annealing the semiconductor substrate to form the metal silicide layer is performed such that the unreacted portion of the metal layer surrounds the metal silicide layer and extends over the top surface of an isolation structure.

### Claim 15 (depends on 13)

The method of claim 13, wherein converting the unreacted portion of the metal layer into the metal oxide layer is performed such that the metal oxide layer is in contact with the top surface of the isolation structure.

### Claim 16 (depends on 12)

The method of claim 12, wherein converting the unreacted portion of the metal layer into the metal oxide layer is performed such that the metal oxide layer has a first portion surrounding the source/drain region and a second portion connected with the first portion, wherein the second portion of the metal oxide layer extends laterally from the first portion away from the source/drain region.

### Claim 17 (depends on 12)

The method of claim 12, wherein forming the source/drain region is performed such that the source/drain region is over a plurality of fins protruding from the semiconductor substrate.

### Claim 18 (depends on 12)

The method of claim 12, wherein removing the metal oxide layer is performed by changing the positive bias to a negative bias.

### Claim 19 (depends on 14)

The method of claim 14, wherein converting an unreacted portion of the metal layer into the metal oxide layer and removing the metal oxide layer are performed in an electrolyte bath.

### Claim 20 (depends on 12)

The method of claim 12, wherein the positive bias is larger than 0V and equal to or smaller than 5V.