Semiconductor device and formation method thereof
AssigneesSemiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
InventorFei ZHOU
Life of this patent
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Abstract
Semiconductor device and fabrication method are provided. A plurality of spaced-apart fins is formed on a substrate. A dummy gate structure is formed across the fins over the substrate. A first interlayer dielectric layer is formed on the substrate and on a sidewall of the dummy gate structure, and a top of the first interlayer dielectric layer is lower than a top of the dummy gate structure and higher than a top of the fins. A cut-out opening, according to a cut-out pattern, is formed through the dummy gate structure and between adjacent fins. A second interlayer dielectric layer is formed on the first interlayer dielectric layer and fills in the cut-out opening.
Claims20
A method of forming a semiconductor device, comprising:
- providing a substrate;
- forming a plurality of spaced-apart fins on the substrate;
- forming a dummy gate structure across the fins over the substrate;
- forming a first interlayer dielectric layer on the substrate and on a sidewall of the dummy gate structure, wherein a top of the first interlayer dielectric layer is lower than a top of the dummy gate structure and higher than the top of the fins;
- forming a cut-out opening, according to a cut-out pattern, passing through the dummy gate structure and between adjacent fins;
- and
- forming a second interlayer dielectric layer on the first interlayer dielectric layer and filling in the cut-out opening with the second interlayer dielectric layer.
A semiconductor device, comprising:
- a substrate;
- a plurality of spaced-apart fins on the substrate;
- a dummy gate structure across the fins over the substrate, wherein the dummy gate structure includes a cut-out opening between adjacent fins;
- a first interlayer dielectric layer on the substrate and on a sidewall of the dummy gate structure, wherein a top of the first interlayer dielectric layer is lower than a top of the dummy gate structure and higher than a top of the fins;
- and
- a second interlayer dielectric layer on the first interlayer dielectric layer and filling in the cut-out opening through the dummy gate structure between the adjacent fins.
Dependencies are inferred from the claim text.