Non-volatile memory device

A memory device, comprising:

• a semiconductive substrate comprising a source region, a drain region, and a channel region between the source region and the drain region;
• a select gate over and vertically spaced apart from a first portion of the channel region;
• and
• a floating gate over and vertically spaced apart from a second portion of the channel region and laterally spaced apart from the select gate, wherein a bottommost portion of the floating gate is lower than a topmost portion of the drain region.

A integrated circuit, comprising:

• a semiconductive substrate;
• a memory device comprising:
• a source region and a drain region within the semiconductive substrate;
• a channel region within the semiconductive substrate and between the source region and the drain region;
• a select gate over and vertically spaced apart from a first portion of the channel region;
• and
• a floating gate over and vertically spaced apart from a second portion of the channel region and laterally spaced apart from the select gate, wherein the memory device is free of a control gate over the floating gate.