Resistive memory device with trimmable driver and sinker and method of operations thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChung-Cheng CHOU
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Abstract
A device is disclosed. The device includes a first memory cell, a second memory cell, a first pair of a driver and a sinker, and a second pair of a driver and a sinker. The first memory cell is coupled between the first pair of the driver and the sinker through a first line and a second line. The second memory cell is coupled between the second pair of the driver and the sinker through a third line and a fourth line. The first pair of the driver and the sinker are configured to be controlled to have resistances depending on a row location of the first memory cell in a memory column.
Claims20
A device, comprising:
- a first memory cell and a second memory cell;
- a first pair of a driver and a sinker, wherein the first memory cell is coupled between the first pair of the driver and the sinker through a first line and a second line;
- and
- a second pair of a driver and a sinker, wherein the second memory cell is coupled between the second pair of the driver and the sinker through a third line and a fourth line;
- wherein the first pair of the driver and the sinker are configured to be controlled to have resistances depending on a row location of the first memory cell in a memory column.
A device, comprising:
- a memory cell in a first column and a reference cell in a second column, wherein the reference cell is coupled to the memory cell through a word line;
- and
- a reference resistor coupled to the reference cell and configured to operate in response to a driving voltage, wherein the driving voltage is associated with a preset voltage and a feedback voltage that is generated when a current flows through a first resistor,
- wherein the reference resistor comprises a second resistor, and the first and second resistors are controlled to have a resistance which equals a median value of a low state resistance and a high state resistance of the memory cell.
A method, comprising:
- selectively, according to a row location of a memory cell in a column, conducting a number of a plurality of first parallel-connected MOS transistors of a first type and a number of a plurality of second parallel-connected MOS transistors of a second type,
- wherein the memory cell is coupled between the plurality of first and second parallel-connected MOS transistors through a first line and a second line;
- wherein when the memory cell approaches the plurality of first parallel-connected MOS transistors, the number of the plurality of first parallel-connected MOS transistors being conducted is different from the number of the plurality of second parallel-connected MOS transistors being conducted.
Dependencies are inferred from the claim text.