Dynamic Power Reduction in SRAM
AssigneeAmbient Scientific, Inc.
InventorGajendra Prasad SINGH
Life of this patent
Estimating the term…
Abstract
A circuit for reducing dynamic power in SRAM and methods for using the same are disclosed. In one embodiment, a circuit for reducing dynamic power in SRAM includes a plurality of memory blocks, which includes a plurality memory banks, which in turn includes a plurality bit cells; a set of memory bank signal lines; a set of memory block signal lines shared across the plurality of memory banks in the memory block; a bridge circuit couple between the set of memory bank signal lines and the set of memory block signal lines; a set of sense amplifiers corresponding to the set of memory block signal lines, where the set of sense amplifiers are shared among the plurality of memory banks in the memory block; and a controller configured to control an access of one or more bit cells in the plurality bit cells.
Claims20
A circuit for reducing dynamic power in SRAM, comprising:
- a plurality of memory blocks, wherein a memory block in the plurality of memory blocks includes a plurality memory banks, wherein a memory bank in the plurality of memory banks includes a plurality bit cells;
- a set of memory bank signal lines, wherein a bit cell in the memory bank is accessed through the set of memory bank signal lines;
- a set of memory block signal lines shared across the plurality of memory banks in the memory block;
- a bridge circuit couple between the set of memory bank signal lines and the set of memory block signal lines;
- a set of sense amplifiers corresponding to the set of memory block signal lines, wherein the set of sense amplifiers are shared among the plurality of memory banks in the memory block;
- and
- a controller configured to control an access of one or more bit cells in the plurality bit cells.
A method for reducing dynamic power in SRAM, comprising:
- providing a plurality of memory blocks, wherein a memory block in the plurality of memory blocks includes a plurality memory banks, wherein a memory bank in the plurality of memory banks includes a plurality bit cells;
- providing a set of memory bank signal lines, wherein a bit cell in the memory bank is accessed through the set of memory bank signal lines;
- sharing a set of memory block signal lines across the plurality of memory banks in the memory block;
- bridging, by a bridge circuit, between the set of memory bank signal lines and the set of memory block signal lines;
- sharing a set of sense amplifiers among the plurality of memory banks in the memory block, wherein the set of sense amplifiers correspond to the set of memory block signal lines;
- and
- controlling, by a controller, an access of one or more bit cells in the plurality bit cells.
Dependencies are inferred from the claim text.