Static Power Reduction in SRAM
AssigneeAmbient Scientific, Inc.
InventorGajendra Prasad SINGH
Life of this patent
Estimating the term…
Abstract
A circuit for reducing static power in SRAM and methods for using the same are disclosed. In one embodiment, a circuit for reducing static power in SRAM includes a plurality of memory blocks, where a memory block in the plurality of memory blocks includes a plurality memory banks, where a memory bank in the plurality of memory banks includes a plurality bit cells. The circuit further includes a bias circuit configured to produce a bias voltage to a row of bit cells, where the bias circuit is coupled to a circuit ground terminal of the row of bit cells in the plurality of bit cells, and a controller configured to control the bias circuit to produce a first set of bias settings in an access mode and control the bias circuit to produce a second set of bias settings in a standby mode of the SRAM.
Claims16
A circuit for reducing static power in SRAM, comprising:
- a plurality of memory blocks, wherein a memory block in the plurality of memory blocks includes a plurality memory banks, wherein a memory bank in the plurality of memory banks includes a plurality bit cells;
- a bias circuit configured to produce a bias voltage to a row of bit cells, wherein the bias circuit is coupled to a circuit ground terminal of the row of bit cells in the plurality of bit cells in each row of a memory bank;
- and
- a controller configured to control the bias circuit to produce a first set of bias settings in an access mode and control the bias circuit to produce a second set of bias settings in a standby mode of the SRAM, wherein the first set of bias settings are different from the second set of bias settings.
A method for reducing static power in SRAM, comprising:
- providing a plurality of memory blocks, wherein a memory block in the plurality of memory blocks includes a plurality memory banks, wherein a memory bank in the plurality of memory banks includes a plurality bit cells;
- producing, by a bias circuit, a bias voltage to a row of bit cells, wherein the bias circuit is coupled to a circuit ground terminal of the row of bit cells in the plurality of bit cells in each row of a memory bank;
- and
- controlling, by a controller, the bias circuit to produce a first set of bias settings in an access mode and control the bias circuit to produce a second set of bias settings in a standby mode of the SRAM, wherein the first set of bias settings are different from the second set of bias settings.
Dependencies are inferred from the claim text.