Efuse memory cell and efuse memory, and write/read methods thereof

An efuse memory, comprising:

• a plurality of read word lines;
• a plurality of write word lines;
• a plurality of read bit lines;
• a plurality of write bit lines;
• and
• a plurality of efuse memory cells, arranged in M rows and N columns, and M and N are positive integers, wherein:
• each of the plurality of efuse memory cells includes:
• a write bit line terminal;
• a read bit line terminal;
• a read word line terminal;
• a write word line terminal;
• an electric fuse, having a first terminal and a second terminal, wherein the first terminal of the electric fuse is connected to the write bit line terminal;
• a first control transistor, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first control transistor is connected to the second terminal of the electric fuse, the second terminal of the first control transistor is connected to the read bit line terminal, and the control terminal of the first control transistor is connected to the read word line terminal;
• and
• a second control transistor, having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second control transistor is connected to the second terminal of the electric fuse, the second terminal of the second control transistor is a ground terminal, and the control terminal of the second control transistor is connected to the write word line terminal;
• the read word line terminal of each of the plurality of efuse memory cells in a same row is connected to a same read word line, and the write word line terminal of each of the plurality of efuse memory cells in the same row is connected to a same write word line, wherein the same read word line is one of the plurality of read word lines, and the same write word line is one of the plurality of write word lines;
• and
• the read bit line terminal of each of the plurality of efuse memory cells in a same column is connected to a same read bit line, and the write bit line terminal of each of the plurality of efuse memory cells in the same column is connected to a same write bit line, wherein the same read bit line is one of the plurality of read bit lines, and the same write bit line is one of the plurality of write bit lines.