Main word line driver circuit

A main word line circuit for a memory device, comprising:

• a RF driver circuit configured to provide a first row factor signal and a second row factor signal;
• a main word line driver circuit including,
• a pull-up circuit configured to receive the first row factor signal and a first decoded address signal, the pull-circuit further configured to drive a global word line to follow the first decoded address signal when the first row factor signal is at a first value and isolate the first decoded address signal from the global word line signal when the first row factor signal is at a second value, and
• an intermediate voltage circuit configured to receive the first decoded address signal and the first and second row factor signals, the intermediate circuit further configured to drive the global word line to follow a value of the second row factor signal;
• and
• a processing device operatively coupled to the RF driver circuit, the processing device configured to,
• drive the global word line to an active state by setting the first row factor signal to the first value when the first decoded address signal is at a high state, and
• drive the global word line to follow a value of the second row factor signal by setting the first row factor signal to the second value while the first decoded address signal is at the high state,
• wherein the value of the second row factor signal is at an intermediate voltage level that is below a voltage level of the active state and above a voltage level of a pre-charge state.