Memory component with staggered power-down exit
AssigneeRambus Inc.
InventorsIan Shaeffer, Lei Luo, Liji Gopalakrishnan
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
Claims21
1-20. (canceled)
A method of operation within an integrated-circuit memory component (“memory IC”), the method comprising:
- receiving, via a first clock input, a command/address clock signal that toggles continuously throughout a first interval at a first frequency;
- receiving, via a second clock input, a data clock signal that toggles at a second frequency at least twice the first frequency;
- during an initial portion of the first interval while distribution of the data clock signal within a data interface is disabled, receiving a memory access command synchronously with respect to the command/address clock signal;
- and
- enabling distribution of the data clock signal within the data interface of the memory IC during a latter portion of the first interval in response to receiving the memory access command.
An integrated-circuit memory component (“memory IC”) comprising:
- a first clock input to receive a command/address clock signal that toggles continuously throughout a first interval at a first frequency;
- a second clock input to receive a data clock signal that toggles at a second frequency at least twice the first frequency;
- a command/address interface to receive, during an initial portion of the first interval while distribution of the data clock signal within the data interface is disabled, a memory access command synchronously with respect to the command/address clock signal;
- and
- control circuitry to enable distribution of the data clock signal within the data interface of the memory IC during a latter portion of the first interval in response to receiving the memory access command.
An integrated-circuit memory component (“memory IC”) comprising:
- means for receiving a command/address clock signal that toggles continuously throughout a first interval at a first frequency;
- means for receiving a data clock signal that toggles at a second frequency at least twice the first frequency;
- means for receiving, during an initial portion of the first interval while distribution of the data clock signal within the data interface is disabled, a memory access command synchronously with respect to the command/address clock signal;
- and
- means for enabling distribution of the data clock signal within the data interface of the memory IC during a latter portion of the first interval in response to receiving the memory access command.
Dependencies are inferred from the claim text.