Memory system and method of operating the memory system
AssigneeSK hynix Inc.
InventorsChang Kyun PARK, Young Sik KOH, Seung Jin PARK, Dong Hyun LEE
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Abstract
The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller configured to generate a command for controlling the memory device and output the command to the memory device. The interface circuit receives the command, transmits the received command to the semiconductor memory when the received command corresponds to the semiconductor memory, and performs a training operation of the interface circuit when the received command corresponds to the interface circuit and the received command is a specific command.
Claims20
A memory system comprising:
- a memory device including an interface circuit and a semiconductor memory;
- and
- a controller configured to generate a command for controlling the memory device and output the command to the memory device,
- wherein the interface circuit receives the command, transmits the received command to the semiconductor memory when the received command corresponds to the semiconductor memory, and performs a training operation of the interface circuit when the received command corresponds to the interface circuit and the received command is a specific command.
A memory system comprising:
- a controller configured to generate and output a first command or a second command corresponding to a training operation;
- an interface circuit configured to perform a first training operation thereto in response to the first command, or transfer the second command to a memory device;
- and
- the memory device configured to perform a second training operation in response to the second command.
A method of operating a memory system, the method comprising:
- providing an interface circuit connected between a controller and a semiconductor memory, the interface circuit configured to mediate data communication between the controller and the semiconductor memory;
- generating, by the controller, a first command for a training operation of the interface circuit or a second command for a training operation of the semiconductor memory, and transmitting the first command or the second command to the interface circuit;
- performing, by the interface circuit, the training operation in response to the first command, and blocking, by the interface circuit, transfer of the first command to the semiconductor memory during the training operation of the interface circuit;
- and
- transmitting, by the interface circuit, the second command to the semiconductor memory to perform, by the semiconductor memory, the training operation in response to the second command.
Dependencies are inferred from the claim text.