Page buffer and memory device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsYong Sung CHO, Jeung Hwan PARK, Jong Min KIM, Jung Kwan KIM
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Abstract
A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.
Claims20
A page buffer comprising:
- a plurality of semiconductor elements formed in a first region of a semiconductor substrate and configured to provide a latch connected to at least one of a plurality of bit lines through a sensing node;
- a first latch signal line disposed on a first level in the first region and connected to a first node of the latch;
- a second latch signal line disposed on the first level and connected to a second node of the latch, wherein a voltage of the first node and a voltage of the second node are complementary;
- a sensing line disposed between the first latch signal line and the second latch signal line on the first level, and configured to provide the sensing node;
- and
- a data transfer line disposed adjacent to the first latch signal line on the first level,
- wherein the first latch signal line, the second latch signal line, the sensing line, and the data transfer line extend in a first direction,
- wherein the plurality of semiconductor elements comprise a pass transistor having active regions connected to the data transfer line, and transistors disposed adjacent to the pass transistor and connected to the pass transistor in series.
A page buffer comprising:
- a first data transfer line;
- a pass transistor configured to set a connection between the first data transfer line and a second data transfer line of another page buffer;
- a plurality of latches connected to the first data transfer line and configured to exchange data with each other through the first data transfer line;
- and
- a control logic configured to activate the pass transistor to connect the first and second data transfer lines during a data identification mode and deactivate the pass transistor to disconnect the first and second data transfer lines during exchange of the data between the plurality of latches.
A memory device comprising:
- a memory cell region including a first metal pad;
- a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
- a memory cell array in the memory cell region having a plurality of memory cell strings, and a plurality of bit lines connected to the plurality of memory cell strings;
- a plurality of page buffers in the peripheral circuit region connected to the plurality of bit lines;
- and,
- a monitoring circuit in the peripheral circuit region connected in a wired OR configuration to at least some page buffers from among the plurality of page buffers responsive to activation of pass transistors included in the at least some page buffers,
- wherein each of the plurality of page buffers comprises
- a plurality of latches sharing a data transfer node and configured to exchange data with each other through the data transfer node, and
- a pass transistor configured to set a connection between the data transfer node and another data transfer node another page buffer from among the plurality of page buffers.
Dependencies are inferred from the claim text.