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US 2020/0349984 A1Published application
Semiconductor package configuration for reduced via and routing layer requirements
AssigneeWestern Digital Technologies, Inc.
InventorsTenzin Namgyal Maja, Rohith V Kamath
Life of this patent
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Abstract
Semiconductor packages are mounted opposite one another across a printed circuit board, where one of the packages is configured with a mirrored pin assignment of the other.
Claims15
An apparatus comprising:
- a printed circuit board;
- a first semiconductor package comprising a plurality of pins mounted on a first side of the printed circuit board;
- and
- a second semiconductor package mounted on a second side of the printed circuit board opposite the first side, the second semiconductor package comprising a mirrored pin assignment of the first semiconductor package.
1 more element
A memory device comprising:
- at least two NAND memory packages mounted pairwise opposite one another on a printed circuit board;
- and
- one of the NAND memory packages of each pair comprising a mirrored pin assignment of the other of the NAND memory packages of the pair.
An apparatus comprising:
- control means;
- and
- means for mounting a first semiconductor package and a second semiconductor package, each comprising at least 170 pins, opposite one another on a printed circuit board, such that routing from the control means to each semiconductor package utilizes a single via per pin and only two routing layers in the printed circuit board.
Dependencies are inferred from the claim text.