Mipi d-phy circuit

Abstract

The present disclosure discloses a MIPI D-PHY circuit, which comprises a main control module, a controlled module, an internal data source generating module, and a configuration register. The main control module and the controlled module are respectively connected to the configuration register, and the main control module is connected to the internal data source generating module. The main control module and the controlled module comprise a clock channel and a data channel respectively. The clock channel and the data channel in the main control module and the data channel and the clock channel in the controlled module both comprise an error detection unit. The MIPI D-PHY circuit provided by the present disclosure adopts the error detection unit to detect the signals of the main control module and the controlled module, and the high-speed serial-parallel conversion and the high-speed parallel-serial conversion are realized by digital circuits, which reduces the area of the D-PHY circuit and reduces the complexity of the whole circuit.

Dependencies are inferred from the claim text.