High bandwidth memory system

A system, comprising:

• a processor;
• a high-bandwidth memory (HBM);
• and
• a controller that includes a memory, the controller:
• receiving a data write request from the processor,
• storing, a first entry in the memory of the controller indicating at least one address of data of the data write request based on data of the data write request comprising sparse data in which sparse data comprises a predetermined percentage of data values of data of the data write request equal to zero, and
• generating an indication that a data bus is available for an operation during a cycle time of the data write request based on the data write request comprising sparse data.

A method, comprising:

• receiving, at a controller of a high-bandwidth memory (HBM), a data write request from a processor external to the HBM;
• storing, by the controller, a first entry in a memory of the controller that indicates at least one address of data of the data write request based on data of the data write request comprising sparse data;
• and
• generating, by the controller, an indication that a data bus is available for an operation during a cycle time of the data write request based on data of the data write request comprising sparse data,
• wherein sparse data comprises a predetermined percentage of data values of data of the data write request equal to zero.