Selective enforcement of hardware-based cache coherency
AssigneeHewlett Packard Enterprise Development LP
InventorsThomas McGee, Michael S. Woodacre, Michael Malewicki
Life of this patent
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Abstract
In exemplary aspects of enforcing cache coherency, a request is received from a node controller, to process a cache coherent operation on a memory block in a shared memory. Based on the information included in the request, a determination is made as to whether the request was transmitted from a processor that is remote relative to the memory that includes the memory block referenced in the request. If the request is from a remote processor, the hardware-based cache coherency of the system is disabled. Instead, the request is processed according to software-based cache coherency mechanisms. A response to the request is transmitted to the requestor.
Claims18
An apparatus comprising:
- one or more hardware components associated with at least a first processor and at least a first memory and operable to enforce hardware-based cache coherency for memory blocks of the at least the first memory,
- wherein the one or more hardware components are configured to:
- receive a first request from a node controller, the first request being a request to process a cache coherent operation, the first request including at least a request type and a memory address of a memory block in the first memory;
- determine that the first request is from a remote processor;
- disable the enforcement of hardware-based cache coherency;
- process the first request, the processing of the first request including at least causing the execution of software to enforce software-based cache coherency;
- and
- transmit, to the node controller, a response to the first request.
A computer-implemented method comprising:
- receiving, by a first node controller, a first request from a second node controller, the first node controller being associated with at least a first processor and at least a first memory, and being operable to enforce hardware-based cache coherency for memory blocks of the at least the first memory,
- wherein the first request is a request to process a cache coherent operation, and the first request includes at least a request type and a memory address of a memory block in the first memory;
- determining, by the first node controller that the first request is from a remote processor;
- disabling the enforcement of hardware-based cache coherency;
- processing the first request, the processing of the first request including at least causing the execution of software to enforce software-based cache coherency;
- and
- transmitting, to the second node controller, a response to the first request.
A system comprising:
- a plurality of communicatively coupled node controllers, each of the node controllers being associated with and managing cache coherency of respective processors and memories,
- wherein each of the node controllers includes hardware components configured to:
- identify whether coherent operation requests are from remote processors or local processors;
- process the coherent operation requests based on the determination of whether the coherent operation requests are from local processors or remote processors,
- wherein, the processing of the coherent operation requests received from local processors includes enforcing hardware-based cache coherency, and the processing of the coherent operation requests received from remote processors includes disabling hardware-based cache coherency and enforcing software-based cache coherency.
Dependencies are inferred from the claim text.