Systems and methods for performing matrix compress and decompress instructions

A processor comprising:

• fetch circuitry to fetch a decompress instruction whose format has fields to specify an opcode and locations of compressed source and decompressed destination matrices;
• decode circuitry to decode the fetched decompress instructions;
• and
• execution circuitry, responsive to the decoded decompress instruction, to:
• generate a decompressed result according to a decompress algorithm by, when the specified compressed source matrix comprises packed non-zero-valued elements, copying each element of the specified source matrix to its associated position within the specified decompressed destination matrix, the associated position being identified by a multi-bit header having one bit per element of the specified decompressed destination matrix, with bits corresponding to non-zero-valued elements being set;
• and
• store the decompressed result to the specified decompressed destination matrix.

A method to be performed by a processor, the processor to:

• fetch, using fetch circuitry, a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices;
• decode, using decode circuitry, the fetched compress instructions;
• and
• respond, using execution circuitry, to the decoded compress instruction, by:
• generating a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits;
• and
• storing the compressed result to the specified compressed destination matrix.