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US 2020/0348936 A1Published application
Method of managing multi-tier memory displacement using software controlled thresholds
AssigneeIntel Corporation
InventorsHarshad S. SANE, Anup MOHAN, Kshitij A. DOSHI, Mark A. SCHMISSEUR
Life of this patent
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Abstract
A computing system includes a memory controller having a plurality of bypass parameters set by a software program, a thresholds matrix to store threshold values selectable by the plurality of bypass parameters, and a bypass function to determine whether a first cache line is to be displaced with a second cache line in a first memory or the first cache line remains in the first memory and the second cache line is to be accessed by at least one of a processor core and the cache from a second memory.
Claims27
An apparatus comprising:
- at least one processor core circuitry to execute instructions of a program;
- a cache;
- and
- memory controller circuitry including
- a plurality of bypass parameters set by the program;
- a thresholds matrix to store threshold values selectable by the plurality of bypass parameters;
- and
- a bypass function to determine whether a first cache line is to be displaced with a second cache line in a first memory or the first cache line remains in the first memory and the second cache line is to be accessed by at least one of the processor core circuitry and the cache from a second memory.
5 more elements
A computer system comprising:
- a first memory;
- a second memory;
- at least one processor core circuitry to execute instructions of a program;
- a cache;
- and
- memory controller circuitry including
- a plurality of bypass parameters set by the program;
- a thresholds matrix to store threshold values selectable by the plurality of bypass parameters;
- and
- a bypass function to determine whether a first cache line is to be displaced with a second cache line in the first memory or the first cache line remains in the first memory and the second cache line is to be accessed by at least one of the processor core circuitry and the cache from the second memory.
7 more elements
A method comprising:
- receiving, by memory controller circuitry, a plurality of bypass parameters from a program being executed by a processor core;
- determining a total evictions rate;
- determining a dirty eviction rate;
- determining a state of whether a second cache line is clean or dirty;
- selecting a threshold value from a thresholds matrix based at least in part on a selected one of the bypass parameters;
- and
- determining whether a first cache line is to be displaced with the second cache line in a first memory or the first cache line remains in the first memory and the second cache line is to be accessed by at least one of the processor core and the cache from a second memory.
4 more elements
Dependencies are inferred from the claim text.