Back to results
US 2020/0348909 A1Published application
Scalable matrix node engine with configurable data formats
AssigneeTesla, Inc.
InventorsDebjit Das Sarma, William McGee, Emil Talpes
Life of this patent
Estimating the term…
Abstract
A microprocessor system comprises a matrix computational unit and a control unit. The matrix computational unit includes one or more processing elements. The control unit is configured to provide a matrix processor instruction to the matrix computational unit. The matrix processor instruction specifies a floating-point operand formatted with an exponent that has been biased with a specified bias.
Claims20
A microprocessor system, comprising:
- a matrix computational unit that includes one or more processing elements;
- and
- a control unit configured to provide a matrix processor instruction to the matrix computational unit, wherein the matrix processor instruction specifies a floating-point operand formatted with an exponent that has been biased with a specified bias.
A microprocessor system, comprising:
- a matrix processor, wherein the matrix processor is configured to receive a matrix processor instruction that specifies a floating-point operand formatted with an exponent that has been biased with a specified bias;
- a post-processing unit;
- a control unit configured to provide a post-processing instruction to the post-processing unit and the matrix processor instruction to the matrix processor;
- and
- a post-processing register file, wherein the post-processing instruction specifies an operand stored in the post-processing register file.
2 more elements
A method comprising:
- receiving a matrix processor instruction from a control unit, wherein the matrix processor instruction specifies a floating-point operand formatted with an exponent that has been biased with a specified bias;
- issuing one or more reads for data values of the floating-point operand;
- receiving the data values of the floating-point operand;
- and
- loading one or more received data values into a matrix computational unit.
2 more elements
A method comprising:
- receiving a matrix processor instruction from a control unit, wherein the matrix processor instruction specifies a first floating-point operand and a second floating-point operand;
- loading a first half of the first floating-point operand into a first processing element and a second processing element;
- loading a second half of the first floating-point operand into a third processing element and a fourth processing element;
- loading a first half of the second floating-point operand into the first processing element and the third processing element;
- loading a second half of the second floating-point operand into the second processing element and the fourth processing element;
- determining a first, second, third, and fourth floating-point multiplication result corresponding to each of the first, second, third, and fourth processing elements;
- and
- storing the first, second, third, and fourth floating-point multiplication result in an output accumulator.
5 more elements
Dependencies are inferred from the claim text.