Static power reduction in caches using deterministic naps
AssigneeTexas Instruments Incorporated
InventorsOluleye Olorode, Mehrdad Nourani
Life of this patent
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Abstract
Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.
Claims20
A cache memory system comprising:
- a cache memory operable to store data in a plurality of addresses, the cache memory divided into cache lines and sets of cache lines;
- a first pipeline stage operable to:
- receive a cache access, wherein the cache access includes a set field and a tag field;
- decode the set field to determine a set of cache lines in the cache memory corresponding to the cache access;
- perform a tag read;
- and
- transition the set of cache lines corresponding to the cache access from a low power state to an operating state while the tag read is performed;
- and
- a second pipeline stage operable to:
- compare the tag field with the result of the tag read to determine a cache hit on the cache access;
- and
- access data on the set of cache lines during the determination of the cache hit.
A cache memory system comprising:
- a cache memory operable to store data in a plurality of addresses divided into cache lines and sets of cache lines;
- a first pipeline stage operable to:
- receive a cache access, wherein the cache access includes a set field and a tag field;
- decode the set field to determine a set of cache lines in the cache memory corresponding to the cache access;
- perform a tag read;
- and
- initiate transition of the set of cache lines corresponding to the cache access from a low power state to an operating state while the tag read is performed;
- and
- a second pipeline stage operable to:
- compare the tag field with the result of the tag read to determine a cache hit on the cache access;
- and
- complete the transition of the set of cache lines corresponding to the cache access from the low power state to the operating state during the compare of the tag field with the result of the tag read;
- and
- a third pipeline stage operable to:
- access data on the set of cache lines.
A method comprising:
- receiving a transaction address including a set field and a tag field;
- decoding the set field to determine a set of cache lines in a cache memory corresponding to the transaction address;
- performing a tag read;
- concurrent with the performing the tag read, initiating transition of the set of cache lines corresponding to the transaction address from a low power state to an operating state;
- comparing the tag field with the result of the tag read to determine a cache hit on the transaction address;
- and
- accessing data on the set of cache lines.
Dependencies are inferred from the claim text.