Cell of transmission gate free circuit and integrated circuit layout including the same

A semiconductor standard cell, comprising:

• a plurality of fins extending along side each other along a first direction;
• a plurality of gate electrodes extending along a second direction substantially perpendicular to the first direction;
• and
• a plurality of transistors,
• wherein each of the plurality of transistors is made of at least one of the plurality of fins and at least one of the plurality of gate electrodes,
• each of the plurality of transistors implements at least an AND-OR-Invert (AOI) logic or an OR-AND-Invert (OAI) logic receiving an input data signal and a clock signal, a storage block storing the input data signal, and an output block outputting a data output signal indicative of the stored data, and
• the clock signal is the only clock signal received by the AOI logic or the OAI logic.

An integrated circuit, comprising:

• a first semiconductor standard cell and a second semiconductor standard cell adjacent to each other in a first direction,
• wherein the first semiconductor standard cell comprises:
• a plurality of fins extending along side each other along a first direction;
• a plurality of gate electrodes extending along a second direction substantially perpendicular to the first direction;
• and
• a plurality of transistors made of the plurality of fins and the plurality of gate electrodes,
• wherein the plurality of transistors receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to an input clock signal,
• the input clock signal is only either a clock signal or another clock signal complementary to the clock signal received by the first semiconductor standard cell in an area defined by first semiconductor standard cell, and
• the data input signal, the input clock signal, and the data output signal are transmitted among the plurality of transistors through at least a plurality of electrically conductive wirings.