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US 2020/0287527 A1Published application
Semiconductor devices
AssigneeSK hynix Inc.
InventorWoongrae KIM
Life of this patent
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Abstract
A semiconductor device includes a test clock generation circuit, a test data generation circuit, and a control code generation circuit. The test clock generation circuit delays a clock signal based on a delay selection signal in a test mode to generate a test clock signal. The test data generation circuit delays data to generate test data. The control code generation circuit latches the test data based on the delay selection signal and the test clock signal to generate a control code.
Claims20
A semiconductor device comprising:
- a test clock generation circuit configured to delay a clock signal based on a delay selection signal in a test mode to generate a test clock signal;
- a test data generation circuit configured to delay data to generate test data;
- and
- a control code generation circuit configured to latch the test data based on the delay selection signal and the test clock signal to generate a control code.
1 more element
A semiconductor device comprising:
- a first latched data generation circuit configured to latch test data based on a first delay selection signal and a test clock signal to output as first latched data;
- a second latched data generation circuit configured to latch the test data based on a second delay selection signal and the test clock signal to output as second latched data;
- and
- a mode register configured to store the first and second latched data, and output the stored first latched data and the stored second latched data as a first control code and a second control code, respectively.
1 more element
Dependencies are inferred from the claim text.