# US 2020/0287464 A1 · Counter-based frequency hopping switching regulator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0287464 A1 - Document ID: US20200287464A1 - Status: Published application - Kind: A1 - Application number: 16/292,113 - Filed: 2019-03-04 - Published: 2020-09-10 - Earliest claimed: 2019-03-04 - Assignees: Analog Devices International Unlimited Company - Applicants: Analog Devices International Unlimited Company - Inventors: Danzhu Lu; Langyuan Wang; Jie He - Web page: https://patentgrep.com/patent/US20200287464A1 ## CPC - H02M 3/1588: {comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence)} - H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters - H02M 3/157: with digital control - H02M 3/158: including plural semiconductor devices as final control devices for a single load - H02M 1/0009: {Devices or circuits for detecting current in a converter} - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract This disclosure describes techniques for controlling switching regulator switching operations. The techniques include selecting a given one of a plurality of clock signals based on a control signal. The techniques further include generating, by the switching regulator, an output voltage from an input voltage by controlling one or more switches according to a switching frequency that corresponds to the selected given one of the plurality of clock signals. The techniques further include varying the switching frequency of the switching regulator by changing a value of the control signal, used to select the given one of the plurality of clock signals, according to a given one of a plurality of refresh rate control signals that corresponds to the selected given one of the plurality of clock signals having respective values that correspond to respective ones of the plurality of refresh rate control signals. ## Claims ### Claim 1 A system for controlling switching operations of a switching regulator, the system comprising: clock signal selection circuitry configured to: receive a plurality of clock signals concurrently; and select a given one of the plurality of clock signals based on a control signal; the switching regulator configured to generate an output voltage from an input voltage by controlling one or more switches according to a switching frequency that corresponds to the selected given one of the plurality of clock signals; and control circuitry configured to vary the switching frequency of the switching regulator by changing a value of the control signal, used by the clock signal selection circuitry to select the given one of the plurality of clock signals, according to a given one of a plurality of refresh rate control signals having respective values that correspond to respective ones of the plurality of clock signals, wherein a first of the plurality of refresh rate control signals causes the clock signal to modify which of the plurality of clock signals is selected according to a first rate, and wherein a second of the plurality of refresh rate control signals causes the clock signal to modify which of the plurality of clock signals is selected according to a second rate. ### Claim 2 (depends on 1) The system of claim 1, wherein the clock signal selection circuitry comprises a multiplexer having a plurality of clock signal inputs each coupled to receive a respective one of the plurality of clock signals and a control input coupled to receive the control signal, wherein the clock signal selection circuitry outputs one of the plurality of clock signals as the selected given one of the plurality of clock signals based on the control signal received at the control input. ### Claim 3 (depends on 1) The system of claim 1, wherein the control circuitry comprises a plurality of counters configured to generate respective ones of the plurality of refresh rate control signals based on respective maximum count values, wherein a first counter of the plurality of counters has a first maximum count value corresponding to a first of the plurality of clock signals, and wherein a second counter of the plurality of counters has a second maximum count value corresponding to a second of the plurality of clock signals. ### Claim 4 (depends on 3) The system of claim 3, wherein the plurality of counters is configured to receive the selected given one of the plurality of clock signals and increment or decrement count values based on the received selected given one of the plurality of clock signals. ### Claim 5 (depends on 4) The system of claim 4, wherein the control circuitry is configured to change the value of the control signal in response to determining that a given one of the plurality of counters has reached the maximum count value of the given one of the plurality of counters. ### Claim 6 (depends on 5) The system of claim 5 further comprising counter selection circuitry configured to select, based on the control signal, between outputs of the plurality of counters to generate the control signal based on the selected output, the outputs of the plurality of counters being indicative of the respective counter having reached the respective maximum count value. ### Claim 7 (depends on 3) The system of claim 3, wherein the control circuitry further comprises random number generator circuitry configured to generate a random or pseudorandom number in response to a selected one of the plurality of counters reaching the respective maximum count value. ### Claim 8 (depends on 7) The system of claim 7, wherein the random or pseudorandom number is represented by a plurality of bits, and wherein a most significant bit of the plurality of bits is provided to the clock signal selection circuitry as the control signal when the plurality of clock signals includes only two clock signals. ### Claim 9 (depends on 1) The system of claim 1, wherein the control circuitry comprises a plurality of logic storage elements coupled to another selection circuit, and wherein: a first of the plurality of logic storage elements is configured to output to the another selection circuit a first value of a first of the plurality of refresh rate control signals at an edge of the given one of the plurality of clock signals; a second of the plurality of logic storage elements is configured to output to the another selection circuit a second value of a second of the plurality of refresh rate control signals at the edge of the given one of the plurality of clock signals; and the another selection circuit selects, as an output of the another selection circuit, between the first and second values based on the control signal, the control signal being generated based on the output of the another selection circuit. ### Claim 10 (depends on 9) The system of claim 9, wherein the control circuitry further comprises random number generator circuitry configured to generate a random or pseudorandom number based on the output of the another selection circuit, wherein the random or pseudorandom number is represented by a plurality of bits, and wherein a most significant bit of the plurality of bits is provided to the clock signal selection circuitry as the control signal. ### Claim 11 (depends on 1) The system of claim 1, wherein the control circuitry comprises a logic storage element, another selection circuit, and random number generator circuitry, and wherein: the another selection circuit is configured to select, as an output of the another selection circuit based on the control signal, between a first and a second of the plurality of refresh rate control signals; the output of the another selection circuit causes the random number generator circuitry to generate a random or pseudorandom number represented by a plurality of bits; and the logic storage element is configured to receive a bit from the plurality of bits and output to the another selection circuit the received bit at an edge of the given one of the plurality of clock signals. ### Claim 12 (depends on 1) The system of claim 1 further comprising feedforward compensation circuitry coupled to the switching regulator, the feedforward compensation circuitry being configured to apply current compensation based on the control signal. ### Claim 13 (depends on 12) The system of claim 12, wherein a value of the current compensation is based on a first frequency of a slowest one of the plurality of clock signals and a second frequency of another one of the plurality of clock signals. ### Claim 14 (depends on 13) The system of claim 13, wherein the feedforward compensation circuitry is configured to apply the current compensation when the given one of the plurality of clock signals that is selected is the slowest one of the plurality of clock signals and prevent applying the current compensation when the given one of the plurality of clock signals that is selected is the another one of the plurality of clock signals. ### Claim 15 (depends on 12) The system of claim 12, wherein the feedforward compensation circuitry includes a number of current sources that corresponds to a number of clock signals in the plurality of clock signals. ### Claim 16 A method for controlling switching operations of a switching regulator, the method comprising: receiving a plurality of clock signals concurrently; selecting a given one of the plurality of clock signals based on a control signal; generating, by the switching regulator, an output voltage from an input voltage by controlling one or more switches according to a switching frequency that corresponds to the selected given one of the plurality of clock signals; and varying the switching frequency of the switching regulator by changing a value of the control signal used to select the given one of the plurality of clock signals, according to a given one of a plurality of refresh rate control signals that corresponds to the selected given one of the plurality of clock signals having respective values that correspond to respective ones of the plurality of refresh rate control signals, wherein a first of the plurality of refresh rate control signals causes the clock signal to modify which of the plurality of clock signals is selected according to a first rate, and wherein a second of the plurality of refresh rate control signals causes the clock signal to modify which of the plurality of clock signals is selected according to a second rate. ### Claim 17 (depends on 16) The method of claim 16 further comprising generating respective ones of the plurality of refresh rate control signals based on respective maximum count values of a plurality of counters, wherein a first counter of the plurality of counters has a first maximum count value corresponding to a first of the plurality of clock signals, and wherein a second counter of the plurality of counters has a second maximum count value corresponding to a second of the plurality of clock signals. ### Claim 18 (depends on 16) The method of claim 16 further comprising applying current compensation based on the control signal, such that the current compensation is applied when the given one of the plurality of clock signals that is selected is a slowest one of the plurality of clock signals and is prevented from being applied when the given one of the plurality of clock signals that is selected is a different one of the plurality of clock signals. ### Claim 19 An apparatus for controlling switching operations of a switching regulator, the apparatus comprising: means for receiving a plurality of clock signals concurrently; means for selecting a given one of a plurality of clock signals based on a control signal; means for generating an output voltage from an input voltage by controlling one or more switches according to a switching frequency that corresponds to the selected given one of the plurality of clock signals; and means for varying the switching frequency of the switching regulator by changing a value of the control signal, used to select the given one of the plurality of clock signals, according to a given one of a plurality of refresh rate control signals that corresponds to the selected given one of the plurality of clock signals having respective values that correspond to respective ones of the plurality of refresh rate control signals, wherein a first of the plurality of refresh rate control signals causes the clock signal to modify which of the plurality of clock signals is selected according to a first rate, and wherein a second of the plurality of refresh rate control signals causes the clock signal to modify which of the plurality of clock signals is selected according to a second rate. ### Claim 20 (depends on 19) The apparatus of claim 19 further comprising: means for generating respective ones of the plurality of refresh rate control signals based on respective maximum count values of a plurality of counters, wherein a first counter of the plurality of counters has a first maximum count value corresponding to a first of the plurality of clock signals, and wherein a second counter of the plurality of counters has a second maximum count value corresponding to a second of the plurality of clock signals; and means for applying current compensation based on the control signal, such that the current compensation is applied when the given one of the plurality of clock signals that is selected is a slowest one of the plurality of clock signals and is prevented from being applied when the given one of the plurality of clock signals that is selected is a different one of the plurality of clock signals.