Camouflaged finfet and method for producing same
AssigneeInside Secure
InventorsLap Wai Chow, Bryan J. Wang, James P. Baukus, Ronald P. Cocchi
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Abstract
A camouflaged FinFET is disclosed. The camouflaged FinFET comprises a fin and a gate, disposed over and perpendicular to the fin. The fin includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, the channel region disposed between the source region and the drain region, and a camouflaged fin region of the second conductivity type, the camouflaged Fin region at least partially rendering the camouflaged FinFET in an always-on condition and having a planar layout substantially indistinguishable from a fin region of an uncamouflaged FinFET.
Claims20
A camouflaged application specific integrated circuit (ASIC), comprising
- a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, the plurality of interconnected functional logic cells comprising:
- at least one camouflaged FinFET, comprising a fin having:
- a source region of a first conductivity type;
- a drain region of the first conductivity type;
- a channel region of a second conductivity type, the channel region disposed between the source region and the drain region;
- and
- a camouflaged fin region of the second conductivity type, the camouflaged Fin region at least partially rendering the camouflaged FinFET in an always-on condition and having a planar layout substantially indistinguishable from a fin region of an uncamouflaged FinFET.
A method of forming a camouflaged FinFET, comprising forming a fin, the fin having:
- a source region;
- a drain region;
- a channel region;
- and
- a camouflage region having:
- a source side extension region adjacent to a source side of the channel region;
- a drain side extension region adjacent to the drain side of the channel region;
- a source side span region between the source region and the source side extension region;
- and
- a drain side span region between the drain region and the drain side extension region;
- forming a gate over only the channel region of the FinFET;
- doping the source side extension region and the drain side extension region according to a first conductivity type;
- forming a source side gate spacer over the source side extension region and a drain side gate spacer over the drain side extension region;
- implanting the source side span region and the drain side span region according to the first conductivity type;
- implanting the source region and the drain region according to a second conductivity type;
- and
- forming self-aligned silicide on the fin.
A camouflaged application specific integrated circuit (ASIC), formed by a process comprising process steps of:
- forming a plurality of FinFETs, each FinFET concurrently formed by performing process steps comprising the steps of:
- forming a fin having:
- a source region;
- a drain region;
- a channel region;
- and
- a camouflage region having:
- a source side extension region adjacent to a source side of the channel region;
- a drain side extension region adjacent to the drain side of the channel region;
- a source side span region between the source region and the source side extension region;
- and
- a drain side span region between the drain region and the drain side extension region;
- forming a gate over only the channel region of the FinFET;
- doping the source side extension region and the drain side extension region according to a first conductivity type;
- forming a source side gate spacer over the source side extension region and a drain side gate spacer over the drain side extension region;
- implanting the source side span region and the drain side span region according to the first conductivity type;
- implanting the source region and the drain region according to a second conductivity type;
- and
- forming self-aligned silicide on the fin.
A camouflaged FinFET, comprising:
- a fin having:
- a source region of a first conductivity type;
- a drain region of the first conductivity type;
- a channel region of a second conductivity type, the channel region disposed between the source region and the drain region;
- a camouflaged fin region of the second conductivity type, the camouflaged Fin region at least partially rendering the camouflaged FinFET in an always-on condition and having a planar layout substantially indistinguishable from a fin region of an uncamouflaged FinFET.
- a gate, disposed over and perpendicular to the fin.
Dependencies are inferred from the claim text.