# US 2020/0287016 A1 · Method of fabricating mosfet

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- Number: US 2020/0287016 A1
- Document ID: US20200287016A1
- Status: Published application
- Kind: A1
- Application number: 16/880,019
- Filed: 2020-05-21
- Published: 2020-09-10
- Earliest claimed: 2018-10-23
- Assignees: Nexchip Semiconductor Corporation
- Applicants: Nexchip Semiconductor Corporation
- Inventors: Geeng-Chuan CHERN
- Web page: https://patentgrep.com/patent/US20200287016A1

## CPC

- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/022: {having lightly-doped source or drain extensions selectively formed at the sides of the gates}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/027: {of lateral single-gate IGFETs}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/01322: {the conductor contacting the insulator having a lateral variation in doping, composition or deposition steps}
- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/212: {Through-implantation}
- H10P 30/22: using masks
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating MOSFET is disclosed. In the method, after a gate is formed by etching a deposited undoped or lightly-doped polysilicon layer, with the portions of the gate above channel edge between a channel region and STI region being protected, ions are doped into the remaining gate portion during source/drain implantation. As a result, each of the gate portions above channel edge is constructed of a doped second polysilicon layer stacked with undoped (or lightly-doped) first polysilicon layers, while the remaining gate portion is simply constituted by the doped second polysilicon layer. This can increase a threshold voltage of the MOSFET at channel edge. Optionally, before the gate is formed by etching the polysilicon, the portions of the polysilicon above the channel edge may be protected, followed by doping ions into the remaining portions of the polysilicon.

## Claims

### Claim 1

A method for fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET), comprising:
providing a substrate and forming therein an STI region that delimits an active area which contains a channel region;
successively forming a gate dielectric layer and a polysilicon layer over both the STI region and the active area, wherein the polysilicon layer is a layer of undoped polysilicon, lightly-doped polysilicon or a combination thereof;
defining a portion of the polysilicon layer above an channel edge between the channel region and the STI region as a first polysilicon layer and a remaining portion of the polysilicon layer as a second polysilicon layer, forming a gate by masking at least portions of the first and second polysilicon layers located above the channel region, and etching away the unmasked portions of the first and second polysilicon layers; and
masking a portion of the gate above the channel edge and performing a source/drain (S/D) implantation on both the unmasked portion of the gate and portions of the active area on both sides of the gate to form source and drain regions, wherein ions implanted to form the source and drain regions are of a same conductivity type as ions in the lightly-doped polysilicon, and wherein the first polysilicon layer in the gate is partially unaffected by the S/D implantation while the second polysilicon layer is entirely converted into a polysilicon layer doped with ions implanted in the S/D implantation.

### Claim 2 (depends on 1)

The method of claim 1, wherein before the gate is formed by etching the polysilicon layer, the first polysilicon layer above the channel edge between the channel region and the STI region is masked, and ions are implanted into the second polysilicon layer so that the second polysilicon layer is converted into a doped polysilicon layer, with a partial thickness of the first polysilicon layer above the channel edge remaining unaffected by the implanted ions.

### Claim 3 (depends on 1)

The method of claim 1, wherein the channel edge has a width ranging from 0.8 T to 1.6 T, where T denotes a deposition thickness of the polysilicon layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein masking a portion of the gate above the channel edge comprises masking the portion of the gate above the channel edge with a patterned mask layer in such a manner that the patterned mask layer is precisely aligned with the channel edge, or that the patterned mask layer covers the entire channel edge and also extends over a portion of the active area adjacent the channel edge, or that the patterned mask layer covers a portion of the channel edge and a portion of the active area adjacent the channel edge, and wherein the patterned mask layer is removed after the S/D implantation has been completed.

### Claim 5 (depends on 2)

The method of claim 2, wherein ions implanted inside the polysilicon layer laterally diffuse into the polysilicon layer above the channel edge from both sides of the channel edge by a distance ranging from 0.8 T to 1.6 T, where T denotes a deposition thickness of the polysilicon layer.

### Claim 6 (depends on 2)

The method of claim 2, wherein masking the first polysilicon layer comprises masking the first polysilicon layer above the channel edge with a patterned mask layer in such a manner that the patterned mask layer is precisely aligned with the channel edge, or that the patterned mask layer covers the entire channel edge and also extends over a portion of the active area adjacent the channel edge, or that the patterned mask layer covers a portion of the channel edge and a portion of the active area adjacent the channel edge, and wherein the patterned mask layer is removed after the implantation of the ions has been completed.

### Claim 7 (depends on 1)

The method of claim 1, wherein after the gate is formed, and before the portion of the gate above the channel edge is masked, lightly-doped drain (LDD) regions are formed in the active area on both sides of the gate by implanting ions of a same conductivity type as the ions implanted in the source region.

### Claim 8 (depends on 7)

The method of claim 7, wherein subsequent to the formation of the LDD regions, and prior to the formation of the source and drain regions, spacers are formed on side walls of the gate.

### Claim 9 (depends on 1)

The method of claim 1, wherein subsequent to the formation of the source and drain regions, metal silicides are formed on respective surfaces of the gate, the source region and the drain region.