# US 2020/0287010 A1 · Novel gate feature in finfet device

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- Number: US 2020/0287010 A1
- Document ID: US20200287010A1
- Status: Published application
- Kind: A1
- Application number: 16/881,486
- Filed: 2020-05-22
- Published: 2020-09-10
- Earliest claimed: 2017-07-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Guan-Jie SHEN; Chia-Der Chang; Chih-Hsiung Lin
- Web page: https://patentgrep.com/patent/US20200287010A1

## CPC

- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 50/268: {of silicon-containing layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.

## Claims

### Claim 1

A method for forming a fin field-effect transistor (FinFET), comprising:
forming a fin structure protruding from a surface of a substrate;
exposing an upper portion of the fin structure;
forming a dummy poly layer over the upper portion of the fin structure;
etching an upper side portion of the dummy poly layer using a first etching process;
etching a lower side portion of the dummy poly layer using a second etching process;
removing a remaining portion of the dummy poly layer and the poly footing feature thereby forming a void to expose a central portion and a side portion of the upper portion of the fin structure, wherein the side portion extends beyond a vertical projection of the vertical sidewall; and
filling the void with a high-k dielectric layer to surround a top surface and sidewalls of the central portion and side portion of the upper portion of the fin structure.

### Claim 2 (depends on 1)

The method of claim 1 wherein the second etching process exposes an end portion of the upper portion of the fin and forms a poly footing feature that extends beyond a vertical sidewall of the remaining portion of the dummy poly layer, the method further comprising forming a dielectric layer over the exposed end portion and along the vertical sidewall.

### Claim 3 (depends on 2)

The method of claim 2, further comprising filling the void with a metal gate layer to overlay the high-k dielectric layer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising forming a gate feature to overlay the central portion of the upper portion of the fin structure.

### Claim 5 (depends on 4)

The method of claim 4, wherein the gate feature comprises a gate dielectric layer and at least a metal gate layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the gate dielectric layer comprises a high-k dielectric layer.

### Claim 7 (depends on 4)

The method of claim 4, wherein the gate feature surrounds sidewalls and a top surface of the central portion of the upper portion of the fin structure.

### Claim 8 (depends on 4)

The method of claim 4, wherein the gate feature surrounds sidewalls and a top surface of the side portion of the upper portion of the fin structure.

### Claim 9 (depends on 4)

The method of claim 4, further comprising forming a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature.

### Claim 10 (depends on 4)

The method of claim 4, further comprising forming an oxide layer between the fin structure and the gate feature.

### Claim 11

A semiconductor device, comprising:
a substrate;
a fin structure formed on a substrate; and
a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer,
wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the gate dielectric layer comprises a high-k dielectric layer.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, further comprising a first metal gate layer overlaying the gate dielectric layer, wherein the gate feature comprises one or more metal gate layers, stacked on top to one another, on the first metal gate layer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the gate dielectric layer and the first metal gate layer surround sidewalls and a top surface of the central portion of the fin structure.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, further comprising a pair of source/drain features formed along the fin structure, that are disposed at respective sides of the gate feature.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, further comprising an oxide layer disposed between the fin structure and the gate feature.

### Claim 17

A semiconductor device, comprising:
a substrate;
a fin structure formed on a substrate;
a gate feature that traverses the fin structure to overlay a central portion of the fin structure, wherein the gate feature comprises a gate dielectric layer and at least a metal gate layer; and
undercuts formed in respective portions of the dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend away from respective sidewalls of the gate feature and away from the central portion of the fin structure; and
a pair of source/drain features formed along the fin structure and disposed at respective sides of the gate feature.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, further comprising:
a dielectric layer adjacent to opposite sidewalls of the gate feature; and
an oxide layer disposed between the fin structure and the gate feature, wherein the gate feature further extends along the fin structure to overlay opposite side portions of the fin structure located in respective undercuts

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the gate dielectric layer comprises a high-k dielectric layer.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein the gate dielectric layer and the first metal gate layer surround sidewalls and top surfaces of the central portion and the side portions of the fin structure.