# US 2020/0286995 A1 · High-performance lateral bjt with epitaxial lightly doped intrinsic base > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0286995 A1 - Document ID: US20200286995A1 - Status: Published application - Kind: A1 - Application number: 16/295,672 - Filed: 2019-03-07 - Published: 2020-09-10 - Earliest claimed: 2019-03-07 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Pouya Hashemi; Tak H. Ning; Jeng-Bang Yau - Web page: https://patentgrep.com/patent/US20200286995A1 ## CPC - H10D 62/184: {of lateral BJTs} - H10D 10/061: {of lateral BJTs (of heterojunction BJTs H10D10/021; of thin film BJTs H10D10/041)} - H10D 10/60: Lateral BJTs - H10D 10/80: Heterojunction BJTs - H10D 62/134: {of lateral BJTs} - H10D 62/137: {Collector regions of BJTs} - H10D 62/405: {Orientations of crystalline planes} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract High-performance lateral bipolar junction transistors (BJTs) are provided in which a lightly doped upper intrinsic base region is formed between a lower intrinsic base region and an extrinsic base region. The lightly doped upper intrinsic base region provides two electron paths which contribute to the collector current, IC. The presence of the lightly doped upper intrinsic base region increases the total IC and leads to higher current gain, β, if there is no increase of the base current, IB. ## Claims ### Claim 1 A lateral bipolar junction transistor (BJT) comprising: a lower intrinsic base region composed of a first semiconductor material of a first conductivity type located on a surface of a layer that is composed of at least a partially insulating material; an upper intrinsic base region composed of a second semiconductor material of the first conductivity type located on the lower intrinsic base region, wherein the upper intrinsic base region has a lower dopant concentration than the lower intrinsic base region; an extrinsic base region composed of a third semiconductor material of the first conductivity type located on the upper intrinsic base region, wherein the extrinsic base region has a higher dopant concentration than both the upper and lower intrinsic base regions; an emitter region composed of a fourth semiconductor material of a second conductivity type, opposite the first conductivity type, located laterally adjacent to, and contacting, a first side of the lower intrinsic base region; and a collector region composed of the fourth semiconductor material of the second conductivity located laterally adjacent to, and contacting, a second side of the lower intrinsic base region, which is opposite the first side of the lower intrinsic base region. ### Claim 2 (depends on 1) The lateral BJT of claim 1, further comprising a dielectric spacer located on outermost sidewalls of each of the upper intrinsic base region, and the extrinsic base region, wherein the dielectric spacer has a topmost surface that is coplanar with a topmost surface of the extrinsic base region. ### Claim 3 (depends on 2) The lateral BJT of claim 2, further comprising a permeable dielectric material located between the upper intrinsic base region and the extrinsic base region, wherein the permeable dielectric material contacts an inner sidewall of the dielectric spacer. ### Claim 4 (depends on 1) The lateral BJT of claim 1, further comprising an emitter-side faceted intrinsic base portion composed of the first semiconductor material of the first conductivity type located beneath the emitter region and on the layer that is composed of the at least partially insulating material, and a collector-side faceted intrinsic base portion composed of the first semiconductor material of the first conductivity type located beneath the collector region and on the layer that is composed of the at least partially insulating material. ### Claim 5 (depends on 4) The lateral BJT of claim 4, wherein the emitter-side faceted intrinsic base portion and the collector-side faceted intrinsic base portion have a faceted surface and are spaced apart from the lower intrinsic base region. ### Claim 6 (depends on 1) The lateral BJT of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type. ### Claim 7 (depends on 1) The lateral BJT of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type. ### Claim 8 (depends on 1) The lateral BJT of claim 1, wherein the first, second, third and fourth semiconductor materials are compositionally the same. ### Claim 9 (depends on 1) The lateral BJT of claim 1, wherein the first semiconductor material is compositionally different from at least the second semiconductor material. ### Claim 10 (depends on 9) The lateral BJT of claim 9, wherein the first semiconductor material is compositionally the same as the third semiconductor material, but compositionally different from the fourth semiconductor material. ### Claim 11 (depends on 9) The lateral BJT of claim 9, wherein the first semiconductor material is compositionally different from the third and fourth semiconductor materials. ### Claim 12 (depends on 1) The lateral BJT of claim 1, wherein the extrinsic base region is in direct physical contact with the upper intrinsic base region and the third semiconductor material that provides the extrinsic base region is single crystalline. ### Claim 13 (depends on 3) The lateral BJT of claim 3, wherein the third semiconductor material that provides the extrinsic base region is polycrystalline crystalline. ### Claim 14 (depends on 2) The lateral BJT of claim 2, further comprising a contact level interlayer dielectric (ILD) material located laterally on the emitter region, the collector region and the extrinsic base region. ### Claim 15 (depends on 14) The lateral BJT of claim 14, further comprising an emitter-side contact structure located in the contact level ILD material and contacting a surface of the emitter region, a collector-side contact structure located in the contact level ILD material and contacting a surface of the collector region, and a base contact structure located in the contact level ILD material and contacting a surface of the extrinsic base region. ### Claim 16 A method of forming a lateral bipolar junction transistor (BJT), the method comprising: forming an upper intrinsic base layer composed of a second semiconductor material of a first conductivity type on a surface of a lower intrinsic base layer composed of a first semiconductor material of the first conductivity type, wherein the lower intrinsic base layer is present on a surface of a layer that is composed of at least a partially insulating material; a first patterned material stack on a surface of the upper intrinsic base layer, wherein the first patterned material stack includes at least an extrinsic base region composed of a third semiconductor material of the first conductivity type; patterning the upper intrinsic base layer to provide a second patterned material stack utilizing the first patterned material stack as an etch mask, wherein the second patterned material stack includes at least a remaining portion of the upper intrinsic base layer which defines an upper intrinsic base region, and the extrinsic base region; forming a dielectric spacer along a sidewall of the second patterned material stack and in both an emitter-side and a collector-side of the second patterned material stack; creating a notch into the lower intrinsic base layer that is located on both the emitter-side and the collector-side to provide a faceted intrinsic base portion in both the emitter-side and the collector-side; and forming an emitter region composed of a fourth semiconductor material of a second conductivity type that is opposite the first conductivity type in the emitter-side and a collector region composed of the fourth semiconductor material of the second conductivity type in the collector-side. ### Claim 17 (depends on 16) The method of claim 16, wherein the creating the notch comprises: forming a sacrificial faceted epitaxial semiconductor material in both the emitter-side and the collector-side and on physically exposed portions of the lower intrinsic base layer that are not covered by the dielectric spacer and the patterned material stack; and removing the sacrificial faceted semiconductor material from both the emitter-side and the collector-side, wherein during the removal of the sacrificial semiconductor material the notch is created into the lower intrinsic base layer. ### Claim 18 (depends on 16) The method of claim 16, further comprising further forming a contact level interlayer dielectric (ILD) material located laterally on the emitter region, the collector region and the extrinsic base region. ### Claim 19 (depends on 18) The method of claim 18, further comprising forming an emitter-side contact structure in the contact level ILD material and contacting a surface of the emitter region, a collector-side contact structure in the contact level ILD material and contacting a surface of the collector region, and a base contact structure in the contact level ILD material and contacting a surface of the extrinsic base region. ### Claim 20 (depends on 16) The method of claim 16, wherein the first patterned material stack includes a permeable dielectric material located directly beneath the extrinsic base region, and wherein the fourth semiconductor material that provides the extrinsic base region is a polycrystalline semiconductor material.