# US 2020/0286992 A1 · Source/drain extension regions and air spacers for nanosheet field-effect transistor structures

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2020/0286992 A1
- Document ID: US20200286992A1
- Status: Published application
- Kind: A1
- Application number: 16/291,443
- Filed: 2019-03-04
- Published: 2020-09-10
- Earliest claimed: 2019-03-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Yi Song; Zhenxing Bi; Kangguo Cheng; Chi-Chun Liu
- Web page: https://patentgrep.com/patent/US20200286992A1

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/834: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method of forming a semiconductor structure includes forming a nanosheet stack over a substrate, the nanosheet stack including alternating sacrificial and channel layers, the channel layers providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the nanosheet stack and a portion of the substrate, and forming indents in sidewalls of the sacrificial layers at sidewalls of the vertical fins. The method further includes forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins, the nanosheet extension regions increasing in thickness from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins. The method further includes forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers.

## Claims

### Claim 1

A method of forming a semiconductor structure, comprising:
forming a nanosheet stack over a substrate, the nanosheet stack comprising alternating sacrificial layers and channel layers, the channel layers providing nanosheet channels for one or more nanosheet field-effect transistors;
forming one or more vertical fins in the nanosheet stack and at least a portion of the substrate;
forming indents in sidewalls of the sacrificial layers at vertical sidewalls of the one or more vertical fins;
forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the vertical sidewalls of the one or more vertical fins, the nanosheet extension regions increasing in thickness from a first thickness proximate the indented sidewalls of the sacrificial layers to a second thickness proximate the vertical sidewalls of the one or more vertical fins; and
forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the nanosheet stack comprises forming the channel layers with a first thickness and forming the sacrificial layers with a second thickness less than the first thickness.

### Claim 3 (depends on 2)

The method of claim 2, wherein the channel layers comprise silicon and the sacrificial layers comprise silicon germanium.

### Claim 4 (depends on 3)

The method of claim 3, wherein forming the nanosheet extension regions comprises performing a thermal anneal that drives in germanium from the sacrificial layers to the channel layers.

### Claim 5 (depends on 4)

The method of claim 4, wherein the thermal anneal produces a boundary curve that gradually changes as distance from the indented sidewalls of the sacrificial layers towards the vertical sidewalls of the channel layers increases.

### Claim 6 (depends on 4)

The method of claim 4, wherein performing the thermal anneal comprises rapid thermal processing at a temperature in the range of about 800 degrees Celsius to about 900 degrees Celsius for a duration of approximately ten minutes.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the inner spacers comprises depositing spacer material utilizing atomic layer deposition to pinch off the spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers leaving at least a portion of space defined by the indented sidewalls as the air gaps.

### Claim 8 (depends on 1)

The method of claim 1, further comprising, prior to formation of the indented sidewalls of the sacrificial layers:
forming an isolation layer over at least a portion of a top surface of nanosheet stacks;
forming a dummy gate over a top surface of the isolation layer; and
forming sidewall spacers over a remaining portion of the top surface of the nanosheet stacks surrounding the isolation layer and the dummy gate.

### Claim 9 (depends on 8)

The method of claim 8, further comprising, subsequent to formation of the inner spacers and air gaps, performing a replacement metal gate process to replace the dummy gate and remaining portions of the sacrificial layers with a gate stack.

### Claim 10 (depends on 9)

The method of claim 9, further comprising forming source/drain regions over portions of a top surface of the substrate surrounding the sidewalls of the one or more vertical fins and the nanosheet stack.

### Claim 11 (depends on 10)

The method of claim 10, wherein outer edges of the nanosheet extension regions provide a starting surface for epitaxial growth of the source/drain regions.

### Claim 12 (depends on 1)

The method of claim 1, wherein forming the indents in the sidewalls of the sacrificial layers comprises:
forming first indents in the sidewalls of the sacrificial layers prior to forming the nanosheet extension regions; and
forming second indents in the sidewalls of the sacrificial layers subsequent to forming the nanosheet extension regions;
wherein the air gaps are formed in at least a portion of the space defined by the second indents.

### Claim 13

A semiconductor structure, comprising:
a substrate;
one or more vertical fins disposed over a top surface of the substrate, the one or more vertical fins comprising a first semiconductor layer and a nanosheet channel stack disposed over the first semiconductor layer, the nanosheet channel stack comprising alternating gate stack layers and channel layers providing nanosheet channels for one or more nanosheet field-effect transistors;
the gate stack layers having indented sidewalls;
the channel layers comprising nanosheet extension regions extending from the indented sidewalls of the gate stack layers to the vertical sidewalls of the one or more vertical fins, the nanosheet extension regions increasing in thickness from a first thickness proximate the indented sidewalls of the gate stack layers to a second thickness proximate the vertical sidewalls of the one or more vertical fins;
inner spacers disposed in a first portion of spaces between the nanosheet extension regions, the indented sidewalls of the gate stack layers and the vertical sidewalls of the one or more vertical fins; and
air gaps disposed in a second portion of the spaces between the nanosheet extension regions, the indented sidewalls of the gate stack layers and the vertical sidewalls of the one or more vertical fins.

### Claim 14 (depends on 13)

The semiconductor structure of claim 13, further comprising:
an isolation layer disposed over at least a portion of a top surface of the nanosheet stack;
a gate stack disposed over a top surface of the isolation layer; and
sidewall spacers disposed over a remaining portion of the top surface of the nanosheet stack surrounding the isolation layer and the gate stack.

### Claim 15 (depends on 13)

The semiconductor structure of claim 13, further comprising source/drain regions disposed over portions of the top surface of the substrate surrounding the sidewalls of the one or more vertical fins.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein the nanosheet extension regions have a curved thickness profile that increases from the first thickness to the second thickness from the indented sidewalls of the gate stack layers to the source/drain regions.

### Claim 17

An integrated circuit comprising:
a nanosheet field-effect transistor structure comprising:
a substrate;
one or more vertical fins disposed over a top surface of the substrate, the one or more vertical fins comprising a first semiconductor layer and a nanosheet channel stack disposed over the first semiconductor layer, the nanosheet channel stack comprising alternating gate stack layers and channel layers providing nanosheet channels for one or more nanosheet field-effect transistors;
the gate stack layers having indented sidewalls;
the channel layers comprising nanosheet extension regions extending from the indented sidewalls of the gate stack layers to the vertical sidewalls of the one or more vertical fins, the nanosheet extension regions increasing in thickness from a first thickness proximate the indented sidewalls of the gate stack layers to a second thickness proximate the vertical sidewalls of the one or more vertical fins;
inner spacers disposed in a first portion of spaces between the nanosheet extension regions, the indented sidewalls of the gate stack layers and the vertical sidewalls of the one or more vertical fins; and
air gaps disposed in a second portion of the spaces between the nanosheet extension regions, the indented sidewalls of the gate stack layers and the vertical sidewalls of the one or more vertical fins.

### Claim 18 (depends on 17)

The integrated circuit of claim 17, wherein the nanosheet field-effect transistor structure further comprises:
an isolation layer disposed over at least a portion of a top surface of the nanosheet stack;
a gate stack disposed over a top surface of the isolation layer; and
sidewall spacers disposed over a remaining portion of the top surface of the nanosheet stack surrounding the isolation layer and the gate stack.

### Claim 19 (depends on 17)

The integrated circuit of claim 17, wherein the nanosheet field-effect transistor structure further comprises source/drain regions disposed over portions of the top surface of the substrate surrounding the sidewalls of the one or more vertical fins.

### Claim 20 (depends on 19)

The integrated circuit of claim 19, wherein the nanosheet extension regions have a curved thickness profile that increases from the first thickness to the second thickness from the indented sidewalls of the gate stack layers to the source/drain regions.