# US 2020/0286958 A1 · Three-dimensional memory devices

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2020/0286958 A1
- Document ID: US20200286958A1
- Status: Published application
- Kind: A1
- Application number: 16/542,266
- Filed: 2019-08-15
- Published: 2020-09-10
- Earliest claimed: 2019-03-04
- Assignees: Yangtze Memory Technologies Co., Ltd.
- Applicants: Yangtze Memory Technologies Co., Ltd.
- Inventors: Wenyu Hua; Linchun Wu
- Web page: https://patentgrep.com/patent/US20200286958A1

## CPC

- H10B 41/10: characterised by the top-view layout
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- G11C 11/1657: {Word-line or row circuits}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/10: characterised by the top-view layout
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 88/00: Three-dimensional [3D] integrated devices
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers above the substrate. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally along a serpentine path to separate the memory stack into a first area and a second area. The 3D memory device further includes first channel structures each extending vertically through the first area of the memory stack and including a drain at its upper end, and second channel structures each extending vertically through the second area of the memory stack and including a source at its upper end. The 3D memory device further includes semiconductor connections disposed vertically between the substrate and the memory stack. Each semiconductor connection crosses the slit structure in a plan view to electrically connect a respective pair of first and second channel structures.

## Claims

### Claim 1

A three-dimensional (3D) memory device, comprising:
a substrate;
a memory stack comprising interleaved conductor layers and dielectric layers above the substrate;
a slit structure extending vertically through the memory stack and extending laterally along a serpentine path to separate the memory stack into a first area and a second area;
a plurality of first channel structures, each first channel structure extending vertically through the first area of the memory stack and comprising a drain at its upper end;
a plurality of second channel structures, each second channel structure extending vertically through the second area of the memory stack and comprising a source at its upper end; and
a plurality of semiconductor connections disposed vertically between the substrate and the memory stack, each semiconductor connection crossing the slit structure in a plan view to electrically connect a respective pair of first channel structure and second channel structure.

### Claim 2 (depends on 1)

The 3D memory device of claim 1, wherein the first channel structures and the second channel structures are disposed on different sides of the slit structure in a first direction in which each semiconductor connection extends laterally in the plan view.

### Claim 3 (depends on 2)

The 3D memory device of claim 2, further comprising:
a plurality of drain select gates configured to control the drains of the first channel structures; and
a plurality of source select gates configured to control the sources of the second channel structures,
wherein the drain select gates and the source select gates are disposed on different sides of the memory stack in a second direction perpendicular to the first direction in the plan view.

### Claim 4 (depends on 1)

The 3D memory device of claim 1, wherein in the plan view, the first channel structures are disposed in four rows, and the second channel structures are disposed in four rows.

### Claim 5 (depends on 1)

The 3D memory device of claim 1, wherein each distance between the respective pair of first channel structure and second channel structure is nominally the same.

### Claim 6 (depends on 1)

The 3D memory device of claim 1, wherein the slit structure is filled with a dielectric.

### Claim 7 (depends on 1)

The 3D memory device of claim 1, wherein each of the first channel structures and the second channel structures comprises a semiconductor plug at its lower end in contact with the corresponding semiconductor connection.

### Claim 8 (depends on 7)

The 3D memory device of claim 7, wherein the semiconductor plug and the semiconductor connection each comprises polysilicon.

### Claim 9 (depends on 1)

The 3D memory device of claim 1, further comprising a peripheral device disposed vertically between the substrate and the semiconductor connections.

### Claim 10 (depends on 1)

The 3D memory device of claim 1, wherein edges of the interleaved conductor layers and dielectric layers in a staircase structure of the memory stack along a vertical direction toward the substrate are staggered laterally toward the first and second channel structures.

### Claim 11 (depends on 1)

The 3D memory device of claim 1, wherein each conductor layer of the memory stack comprises a metal.

### Claim 12 (depends on 1)

The 3D memory device of claim 1, further comprising a bonding interface between the substrate and the semiconductor connections.

### Claim 13

A three-dimensional (3D) memory device, comprising:
a slit structure extending along a serpentine path in a plan view; and
an array of memory strings, each memory string comprises:
a first channel structure comprising a source at its upper end;
a second channel structure comprising a drain at its upper end; and
a semiconductor connection connecting lower ends of the first and second channel structures, wherein in the plan view, the semiconductor connection crosses the slit structure, and the source and the drain of the memory string are separated by the slit structure in a column direction.

### Claim 14 (depends on 13)

The 3D memory device of claim 13, wherein a distance between the source and the drain of each memory string in the plan view is nominally the same.

### Claim 15 (depends on 13)

The 3D memory device of claim 13, further comprising:
a plurality of drain select gates configured to control the drains of the array of memory strings; and
a plurality of source select gates configured to control the sources of the array of memory strings,
wherein the drain select gates and the source select gates are separated by the array of memory strings in a row direction.

### Claim 16 (depends on 13)

The 3D memory device of claim 13, wherein every two sources and two drains alternate in each column of the array of memory strings.

### Claim 17 (depends on 13)

The 3D memory device of claim 13, further comprising a plurality of sub-slit structures each connected to the slit structure and extending in a row direction in the plan view.

### Claim 18 (depends on 17)

The 3D memory device of claim 17, wherein the plurality of sub-slit structures are disposed on different sides of the memory stack in the row direction.

### Claim 19 (depends on 17)

The 3D memory device of claim 17, wherein at least one of the sub-slit structures comprises an “H” cut.

### Claim 20

A three-dimensional (3D) memory device, comprising:
a substrate;
a bonding interface above the substrate;
a semiconductor connection above the bonding interface;
a memory stack comprising interleaved conductor layers and dielectric layers above the semiconductor connection;
a first channel structure and a second channel structure each extending vertically through the memory stack, a lower end of the first channel structure and a lower end of the second channel structure being in contact with the semiconductor connection; and
a bit line contact and a source line contact each above and in contact with an upper end of the first channel structure and an upper end of the second channel structure.