# US 2020/0286884 A1 · Method and Device for Electrical Overstress and Electrostatic Discharge Protection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0286884 A1 - Document ID: US20200286884A1 - Status: Published application - Kind: A1 - Application number: 16/878,863 - Filed: 2020-05-20 - Published: 2020-09-10 - Earliest claimed: 2017-03-28 - Assignees: Semtech Corporation - Applicants: Semtech Corporation - Inventors: David J. Rose; William A. Russell; Jonathan Clark - Web page: https://patentgrep.com/patent/US20200286884A1 ## CPC - H10D 89/811: {using FETs as protective elements} - H01C 7/12: Overvoltage protection resistors; Arresters - H02H 3/087: for DC applications - H02H 9/025: {Current limitation using field effect transistors} - H02H 9/041: {using a short-circuiting device} - H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits} - H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) - H10D 89/611: {using diodes as protective elements} - H10W 42/80: protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) - H10D 8/20: Breakdown diodes, e.g. avalanche diodes - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H01C: RESISTORS - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device is protected from electrical overstress (EOS) and electro-static discharge (ESD) events by a series protection circuit electrically coupled in series along the transmission line between a signal source and a load. The series protection circuit includes a first field-effect transistor (FET) electrically coupled in series between the signal source and load. A parallel protection circuit is electrically coupled between the transmission line and a ground node. The parallel protection circuit can include a transient-voltage-suppression (TVS) diode. ## Claims ### Claim 1 A semiconductor device, comprising: a transmission line; a junction field-effect transistor (JFET) coupled in series with the transmission line, wherein a gate terminal of the JFET is electrically coupled to the transmission line; a resistor coupled in series with the transmission line between the JFET and the gate terminal of the JFET; and a parallel protection circuit electrically coupled between the transmission line and a ground node. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein a conduction terminal of the JFET is directly electrically coupled to a first terminal of the resistor and a gate terminal of the JFET is directly electrically coupled to a second terminal of the resistor. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the JFET and parallel protection circuit are disposed within a single semiconductor package. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the parallel protection circuit includes a transient-voltage-suppression (TVS) diode. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the JFET, resistor, and transmission line are coupled in series between a source and a load. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the gate terminal of the JFET is directly coupled to the parallel protection circuit. ### Claim 7 A semiconductor device, comprising: a junction field-effect transistor (JFET); and a resistor comprising a first terminal of the resistor coupled to a conduction terminal of the JFET and a second terminal of the resistor coupled to a gate terminal of the JFET. ### Claim 8 (depends on 7) The semiconductor device of claim 7, wherein the conduction terminal of the JFET is directly electrically coupled to the first terminal of the resistor and the gate terminal of the JFET is directly electrically coupled to the second terminal of the resistor. ### Claim 9 (depends on 7) The semiconductor device of claim 7, wherein the JFET and resistor are coupled in series between a source and a load. ### Claim 10 (depends on 7) The semiconductor device of claim 7, further including a parallel protection circuit coupled to the JFET. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the JFET and parallel protection circuit are within a single semiconductor package. ### Claim 12 (depends on 10) The semiconductor device of claim 10, wherein the parallel protection circuit includes a transient-voltage-suppression (TVS) diode. ### Claim 13 (depends on 10) The semiconductor device of claim 10, wherein the gate terminal of the JFET is directly coupled to the parallel protection circuit. ### Claim 14 A method of making a semiconductor device, comprising: providing a transmission line; coupling a junction field-effect transistor (JFET) in series with the transmission line; coupling a gate terminal of the JFET to the transmission line; and coupling a resistor in series with the transmission line between the JFET and the gate terminal of the JFET. ### Claim 15 (depends on 14) The method of claim 14, wherein the conduction terminal of the JFET is directly electrically coupled to the first terminal of the resistor and the gate terminal of the JFET is directly electrically coupled to the second terminal of the resistor. ### Claim 16 (depends on 14) The method of claim 14, further including coupling the JFET and resistor in series between a source and a load. ### Claim 17 (depends on 14) The method of claim 14, further including coupling a parallel protection circuit to the JFET. ### Claim 18 (depends on 17) The method of claim 17, further including disposing the JFET and parallel protection circuit within a single semiconductor package. ### Claim 19 (depends on 17) The method of claim 17, wherein the parallel protection circuit includes a transient-voltage-suppression (TVS) diode. ### Claim 20 (depends on 17) The method of claim 17, wherein the gate terminal of the JFET is directly coupled to the parallel protection circuit.