# US 2020/0286809 A1 · Carbon-pad thermal-interface materials in multi-die packages

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- Number: US 2020/0286809 A1
- Document ID: US20200286809A1
- Status: Published application
- Kind: A1
- Application number: 16/293,163
- Filed: 2019-03-05
- Published: 2020-09-10
- Earliest claimed: 2019-03-05
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Shushan Gong; James C. Matayabas, JR.
- Web page: https://patentgrep.com/patent/US20200286809A1

## CPC

- H10W 40/25: characterised by their materials
- H10W 40/251: {Organics}
- F28F 21/02: of carbon, e.g. graphite
- H10W 40/226: {characterised by projecting parts, e.g. fins to increase surface area (leadframes for cooling H10W70/461)}
- H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 90/00: Package configurations
- F28D 2021/0029: {Heat sinks}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- F28F: DETAILS OF HEAT-EXCHANGE AND HEAT-TRANSFER APPARATUS, OF GENERAL APPLICATION (water and air traps, air venting F16)
- F28D: HEAT-EXCHANGE APPARATUS, NOT PROVIDED FOR IN ANOTHER SUBCLASS, IN WHICH THE HEAT-EXCHANGE MEDIA DO NOT COME INTO DIRECT CONTACT (fluid heaters having heat generating means and heat transferring means F24H; furnaces F27; details of heat-exchange apparatus of general)

## Abstract

Multi-die semiconductor device packages include a solder thermal interface material for a processor device, and a carbon-pad thermal interface material for a high-bandwidth memory device. Disparate dice are packaged against a heat sink on the device backsides, and on a semiconductor package substrate on the device active surfaces and metallizations.

## Claims

### Claim 1

A semiconductor device package, comprising:
a first semiconductive device on a semiconductor package substrate;
a heat sink contacting the first semiconductive device through a metal alloy thermal interface material (TIM);
a subsequent semiconductive device on the semiconductor package substrate;
a carbon-pad thermal interface material (carbon-pad TIM) contacting the heat sink from a backside of the subsequent semiconductive device, wherein the carbon-pad TIM is configured under compression.

### Claim 2 (depends on 1)

The semiconductor device package of claim 1, wherein the metal alloy TIM is a solder TIM (sTIM).

### Claim 3 (depends on 2)

The semiconductor device package of claim 2, wherein the first semiconductive device contacts the sTIM at a backside metallurgy, and wherein the subsequent semiconductive device contacts the carbon-pad TIM at bulk semiconductive material at a backside.

### Claim 4 (depends on 1)

The semiconductor device package of claim 1, wherein the carbon-pad TIM is configured to sustain a thermal resistance in a range from 0.04 to 0.25° C. cm2/Watt.

### Claim 5 (depends on 1)

The semiconductor device package of claim 1, wherein the carbon-pad TIM includes an organic material interstitially mingled with carbon nanotubes.

### Claim 6 (depends on 1)

The semiconductor device package of claim 1, wherein the carbon-pad TIM includes a fluoropolymer material interstitially mingled with carbon nanotubes.

### Claim 7 (depends on 1)

The semiconductor device package of claim 1, wherein the carbon-pad TIM is under compression, between the heat sink and the subsequent semiconductive device on the semiconductor package substrate.

### Claim 8 (depends on 2)

The semiconductor device package of claim 2, further including a third semiconductive device on the semiconductor package substrate and adjacent the first semiconductive device, wherein the third semiconductive device is contacted by a third thermal interface material, selected from a carbon-pad TIM, an sTIM, an elastomer-pad TIM, a vertically oriented graphitic carbon TIM and a pyrolytic graphite sheet TIM.

### Claim 9 (depends on 1)

The semiconductor device package of claim 1, wherein the first die is a collection of up to four aggregated-die processor dice, wherein the subsequent semiconductive device is a collection of up to four high-bandwidth memory semiconductive devices, and wherein each subsequent die backside is contacted by a carbon-pad TIM.

### Claim 10 (depends on 1)

The semiconductor device package of claim 1:
wherein the first semiconductive is a collection of up to four aggregated-die processor dice;
wherein the subsequent semiconductive device is a collection of up to four high-bandwidth memory semiconductive devices;
wherein each subsequent die backside is contacted by a carbon-pad TIM, further including:
wherein a third die is a collection of up to four semiconductive devices on the substrate die side; and
wherein a third TIM is a carbon-pad TIM in a strip form factor that contacts each of the third semiconductive dice at each third-die on a backside surface.

### Claim 11 (depends on 1)

The semiconductor device package of claim 1:
wherein the first semiconductive device is a collection of up to four aggregated-die processor dice;
wherein the subsequent semiconductive device is a collection of up to four high-bandwidth memory semiconductive devices;
wherein each subsequent semiconductive device backside is contacted by a carbon-pad TIM, further including:
wherein a third semiconductive device is a collection of up to four semiconductive devices on the semiconductor package die side;
wherein a third TIM is a carbon-pad TIM in a strip form factor that contacts each of the third semiconductive devices at each third-die on a backside surface; and
at least one fourth semiconductive device adjacent one of the at least one third semiconductive devices, and wherein the carbon-pad TIM in strip form factor also contacts the at least one fourth semiconductive device on the fourth-semiconductive device on a backside surface.

### Claim 12 (depends on 1)

The semiconductor device package of claim 1, wherein the first semiconductive device is a collection of up to four aggregated-die processor dice, wherein at least two of the aggregated-die processor dice are central-processing unit semiconductive devices, wherein at least one of the aggregated-die processor dice is a graphics-processing unit semiconductive device, and wherein each subsequent device backside is contacted by a carbon-pad TIM at each subsequent-semiconductive device backside surface.

### Claim 13 (depends on 1)

The semiconductor device package of claim 1, wherein the carbon-pad TIM provides a thermal resistance between 0.05 and 0.2° C. cm2/Watt, and wherein the carbon-pad TIM has a bond-line thickness in a range between 250 and 450 micrometer.

### Claim 14 (depends on 1)

The semiconductor device package of claim 1, wherein the first semiconductive device and the subsequent semiconductive device communicate through an embedded multi-die interconnect bridge that is embedded in the semiconductor package substrate.

### Claim 15 (depends on 1)

The semiconductor device package of claim 1, further including:
a third semiconductive device on the semiconductor package substrate and adjacent the first semiconductive device, wherein the third semiconductive device is contacted by a carbon-pad TIM;
wherein the first semiconductive device and the subsequent semiconductive device communicate through an embedded multi-die interconnect bridge that is embedded in the semiconductor package substrate; and
wherein the first semiconductive device and the third semiconductive device communicate through an embedded multi-die interconnect bridge that is embedded in the semiconductor package substrate.

### Claim 16

A computing system, comprising:
a first semiconductive device on a semiconductor package substrate, wherein the first semiconductive device is a processor die;
a heat sink contacting the first semiconductive device at a die backside metallurgy and through a solder thermal interface material (sTIM);
a subsequent semiconductive device on the semiconductor package substrate, wherein the subsequent semiconductive device is a high-bandwidth memory die;
a carbon-pad thermal interface material (carbon-pad TIM) contacting the high-bandwidth memory die at a backside at bulk semiconductive material, wherein the carbon-pad TIM also contacts the heat sink, wherein the carbon-pad TIM is configured under compression from the heat sink;
a third semiconductive device on the semiconductor package substrate, wherein the third semiconductive device is contacted by a carbon-pad TIM at a third-die at a backside at bulk semiconductive material; and
wherein the first, subsequent and third semiconductive devices are part of a chipset.

### Claim 17 (depends on 16)

The computing system of claim 16, wherein the first semiconductive device is a collection of up to four aggregated-die processor dice;
wherein at least one of the up to four aggregated-die processor dice is a central-processing unit, wherein at least one of the up to four aggregated-die processor dice is a graphics-processing unit;
wherein the subsequent semiconductive device is a collection of up to four high-bandwidth memory semiconductive devices;
wherein each subsequent device backside is contacted by a carbon-pad TIM; and
wherein the third semiconductive device is a collection of up to four semiconductive devices.

### Claim 18 (depends on 16)

The computing system of claim 16, wherein the first semiconductive device is a collection of up to four aggregated-die processor dice;
wherein at least one of the up to four aggregated-die processor dice is a central-processing unit, wherein at least one of the up to four aggregated-die processor dice is a graphics-processing unit;
wherein the subsequent semiconductive device is a collection of up to four high-bandwidth memory semiconductive devices;
wherein each subsequent semiconductive device backside is contacted by a carbon-pad TIM; and
wherein the third semiconductive device is a collection of up to four semiconductive devices,
and wherein a strip form-factor carbon-pad TIM contacts each of the third semiconductive devices at bulk semiconductive material on each die backside.

### Claim 19 (depends on 16)

The computing system of claim 16, wherein the carbon-pad TIM includes a fluoropolymer material interstitially mingled with carbon nanotubes.

### Claim 20 (depends on 16)

The computing system of claim 16, the carbon-pad TIM further including:
a thermal resistance between 0.05 and 0.2° C. cm2/Watt;
a bond-line thickness in a range between 250 and 450 micrometer; and
a fluoropolymer material interstitially mingled with carbon nanotubes.

### Claim at position 21

21-22. (canceled)