# US 2020/0286804 A1 · Method and apparatus to control temperature of a semiconductor die in a computer system

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- Number: US 2020/0286804 A1
- Document ID: US20200286804A1
- Status: Published application
- Kind: A1
- Application number: 16/292,218
- Filed: 2019-03-04
- Published: 2020-09-10
- Earliest claimed: 2019-03-04
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: John FALLIN; Daniel J. RAGLAND; Jonathan P. DOUGLAS
- Web page: https://patentgrep.com/patent/US20200286804A1

## CPC

- H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60)
- H10W 40/10: Arrangements for heating
- G06F 1/206: {comprising thermal management}
- G06F 11/0721: {within a central processing unit [CPU]}
- G06F 11/0754: {by exceeding limits}
- G06F 11/1417: {Boot up procedures}
- G06F 11/3024: {where the computing system component is a central processing unit [CPU]}
- G06F 11/3058: {Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206)}
- H10W 40/47: by flowing liquids, e.g. forced water cooling
- G06F 2200/201: Cooling arrangements using cooling fluid
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Circuitry to apply heat to a die while the die junction temperature is below a minimum die junction temperature of an operating die junction temperature range for the die is provided. The circuitry to avoid a system boot failure when the die junction temperature is below the operating die junction temperature range of the die.

## Claims

### Claim 1

An apparatus comprising:
a die to operate in an overclocked mode; and
circuitry to apply supplemental heat to the die while a die junction temperature is below an operating temperature range for the die junction temperature.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the supplemental heat is applied if the die junction temperature is below the operating temperature range for the die junction temperature after liquid nitrogen or liquid helium is applied to the die.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the supplemental heat is removed when the die junction temperature is within the operating temperature range for the die.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the circuitry is included in the die and the die is a System on Chip.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the circuitry includes a microcontroller communicatively coupled to the die.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the die is a central processing unit die and the circuitry is in a chipset die.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the circuitry is in a complex programmable logic device (CPLD).

### Claim 8

A method comprising:
applying power to a die; and
applying supplemental heat to the die while a die junction temperature is below an operating temperature range for the die junction temperature.

### Claim 9 (depends on 8)

The method of claim 8, wherein the supplemental heat is applied prior to start of a boot process if the die junction temperature is below the operating temperature range for the die junction temperature.

### Claim 10 (depends on 9)

The method of claim 9, wherein the supplemental heat is removed when the die junction temperature is within the operating temperature range for the die.

### Claim 11 (depends on 8)

The method of claim 8, wherein the supplemental heat is applied by the circuitry included in the die and the die is a System on Chip.

### Claim 12 (depends on 8)

The method of claim 8, wherein the circuitry includes a microcontroller communicatively coupled to the die.

### Claim 13 (depends on 8)

The method of claim 8, wherein the die is a central processing unit die and the supplemental heat is applied by the circuitry in a chipset die.

### Claim 14 (depends on 8)

The method of claim 8, wherein the supplemental heat is applied by the circuitry in a complex programmable logic device (CPLD).

### Claim 15

A system comprising:
a processor;
a display communicatively coupled to the processor; and
circuitry to apply supplemental heat to the processor while a die junction temperature in the processor is below an operating temperature range for the die junction temperature.

### Claim 16 (depends on 15)

The system of claim 15, wherein the supplemental heat is applied prior to start of a boot process if the die junction temperature is below the operating temperature range for the die junction temperature.

### Claim 17 (depends on 16)

The system of claim 16, wherein the supplemental heat is removed when the die junction temperature is within the operating temperature range for the processor.

### Claim 18 (depends on 15)

The system of claim 15, wherein the circuitry and the processor are in a System on Chip.

### Claim 19 (depends on 15)

The system of claim 15, wherein the circuitry includes a microcontroller communicatively coupled to the die.

### Claim 20 (depends on 15)

The system of claim 15, wherein the circuitry is in a chipset die.