# US 2020/0286771 A1 · Sputtering processing and apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0286771 A1 - Document ID: US20200286771A1 - Status: Published application - Kind: A1 - Application number: 16/795,710 - Filed: 2020-02-20 - Published: 2020-09-10 - Earliest claimed: 2019-03-04 - Assignees: Rokko Systems Pte Ltd - Applicants: Rokko Systems Pte Ltd - Inventors: Jong Jae JUNG; Yun Suk SHIN; Deok Chun JANG - Web page: https://patentgrep.com/patent/US20200286771A1 ## CPC - H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes} - C23C 14/34: Sputtering - C23C 14/50: Substrate holders - H10P 72/741: {the auxiliary support including a cavity for storing a finished or partly finished device during manufacturing or mounting, e.g. for an IC package or for a chip} - H10P 72/7422: {used to protect an active side of a device or wafer} - H10P 72/7426: {used as a support during build up manufacturing of active devices} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04) ## Abstract A process for sputtering a plurality of integrated circuit (“IC”) units, the process having at least the steps of: applying a layer to a holding ring; cutting an array of apertures in the layer; transferring the holding ring to a template positioned within a placement station; aligning the array of apertures with an array of recesses in the template; delivering IC units to the holding ring, each IC unit corresponding to an aligned aperture and recess, and then; applying a sputtering process to the IC units engaged with the holding ring. ## Claims ### Claim 1 A process for sputtering a plurality of integrated circuit (“IC”) units, the process comprising the steps of: applying a layer to a holding ring; cutting an array of apertures in the layer; transferring the holding ring to a template positioned within a placement station; aligning said array of apertures with an array of recesses in said template; delivering IC units to said holding ring, each IC unit corresponding to an aligned aperture and recess, and applying a sputtering process to said IC units engaged with said holding ring. ### Claim 2 (depends on 1) The process according to claim 1, further including the step, between the applying step and the cutting step, of applying a backing layer to said holding ring. ### Claim 3 (depends on 2) The process according to claim 2, wherein the cutting step comprises laser cutting. ### Claim 4 (depends on 3) The process according to claim 3, wherein the delivering step includes engaging the IC units with a picker and disengaging them to transfer to the holding ring. ### Claim 5 (depends on 4) The process according to claim 4, wherein the delivering step includes engaging the IC units with a picker and disengaging them to transfer to the holding ring. ### Claim 6 (depends on 5) The process according to claim 5, wherein the applying step includes placing a double-sided tape to the holding ring. ### Claim 7 (depends on 6) The process according to claim 6, wherein the layer is a double-sided tape and the cutting step includes cutting the double-sided tape and then peeling a backing tape to expose an adhesive surface and remove the cut portions of the double-sided tape. ### Claim 8 (depends on 1) The process according to claim 1, wherein the cutting step comprises laser cutting. ### Claim 9 (depends on 2) The process according to claim 2, wherein the delivering step includes engaging the IC units with a picker and disengaging them to transfer to the holding ring. ### Claim 10 (depends on 8) The process according to claim 8, wherein the delivering step includes engaging the IC units with a picker and disengaging them to transfer to the holding ring. ### Claim 11 (depends on 1) The process according to claim 1, wherein the delivering step includes engaging the IC units with a picker and disengaging them to transfer to the holding ring. ### Claim 12 (depends on 9) The process according to claim 9, wherein the delivering step includes engaging the IC units with a picker and disengaging them to transfer to the holding ring. ### Claim 13 (depends on 10) The process according to claim 10, wherein the delivering step includes engaging the IC units with a picker and disengaging them to transfer to the holding ring. ### Claim 14 (depends on 11) The process according to claim 11, wherein the delivering step includes engaging the IC units with a picker and disengaging them to transfer to the holding ring. ### Claim 15 (depends on 1) The process according to claim 1, wherein the delivering step includes engaging the IC units with a picker and disengaging them to transfer to the holding ring. ### Claim 16 (depends on 1) The process according to claim 1, wherein the applying step includes placing a double-sided tape to the holding ring. ### Claim 17 A placement station comprising: a template having an array of recesses; said template arranged to receive a holding ring having an array of apertures; said apertures and recesses arranged to align so as to receive a plurality of integrated circuit (“IC”) units for sputtering. ### Claim 18 (depends on 17) The placement station according to claim 17, wherein the IC units are ball grid array (“BGA”) chips, said apertures sized to allow solder ball connections of the BGA chips to pass through the aperture but retain the IC portion of the BGA chip.