# US 2020/0286571 A1 · Multi-chip programming for phased array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0286571 A1 - Document ID: US20200286571A1 - Status: Published application - Kind: A1 - Application number: 16/789,974 - Filed: 2020-02-13 - Published: 2020-09-10 - Earliest claimed: 2019-03-08 - Assignees: Analog Devices International Unlimited Company - Applicants: Analog Devices International Unlimited Company - Inventors: Stuart John McCracken; Mohamed El-Nozahi; Mohamed Abdelsalam - Web page: https://patentgrep.com/patent/US20200286571A1 ## CPC - G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G11C 7/1003: {Interface circuits for daisy chain or ring bus memory arrangements} - G11C 7/1093: {Input synchronization} - G11C 19/188: {Organisation of a multiplicity of shift registers, e.g. regeneration, timing or input-output circuits} - G11C 7/1036: {using data shift registers} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Systems and methods for multi-chip programming for phased arrays are provided herein. In certain embodiments, a semiconductor device includes one or more inputs configured to receive frame data, an internal memory configured to store the received frame data, and a shift register configured to receive the frame data and comprising a plurality of shift register bit positions. The device further includes a latch configured to store a command type, a first multiplexor configured to select at least one first bit from the shift register based on the command type and provide the at least one first bit to the latch, an output configured to output the frame data, and a second multiplexor configured to select at least one second bit from the shift register based on the command type and provide the at least one second bit to the output. ## Claims ### Claim 1 A semiconductor device for communication via a serial peripheral interface (SPI), comprising: one or more inputs configured to receive frame data; an internal memory configured to store the received frame data; a shift register configured to receive the frame data and comprising a plurality of shift register bit positions; a latch configured to store a command type; a first multiplexor configured to select at least one first bit from the shift register based on the command type and provide the at least one first bit to the latch; an output configured to output the frame data; and a second multiplexor configured to select at least one second bit from the shift register based on the command type and provide the at least one second bit to the output. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first multiplexor is further configured to select the at least one first bit from a first shift register bit position when the command type indicates that the frame data has a first frame type and select the at least one first bit from a second shift register bit position when the command type indicates that the frame data has a second frame type. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the first frame type is a short format having a first frame length defined by a first number of bits of data and the second frame type is a long format having a second frame length defined by a second number of bits of data, the second number is greater than the first number, and wherein the second shift register bit position has a higher value than the first number. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the second multiplexor is further configured to select the at least one second bit from a first shift register bit position when the command type indicates that the frame data has a first frame type, select the at least one second bit from a second shift register bit position when the command type indicates that the frame data has a second frame type, and select the at least one second bit from a third shift register bit position when the command type indicates that the frame data has a third frame type. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the first frame type is an extra-short format having a first frame length defined by a first number of bits of data, the second frame type is a short format having a second frame length defined by a second number of bits of data, and the third frame type is a long format having a third frame length defined by a third number of bits of data, the second number is greater than the first number and the third number is greater than the second number, wherein the second shift register bit position has a higher value than the first number and the third shift register bit position has a higher value than the second number. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the latch is further configured to receive the command type from the first multiplexor. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the latch is further configured to receive a clock signal and store the command type received from the first multiplexor based on an edge of the clock signal. ### Claim 8 (depends on 6) The semiconductor device of claim 6, wherein the latch is further configured to receive an enable signal and a clock signal and store the command type received from the first multiplexor based on an edge of the clock signal and in response to receiving the enable signal. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the one or more inputs are configured to receive the frame data indirectly from a master semiconductor device via a slave semiconductor device. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the one or more inputs and the output are configured to be connected to a plurality of slave semiconductor devices in either a parallel configuration or a series configuration. ### Claim 11 A semiconductor device, comprising: a first input configured to receive a clock signal; a second input configured to receive frame data; a third include configured to receive a semiconductor device select signal; a shift register configured to receive the frame data; and an internal memory configured to store the received data, wherein, the frame data comprises one or more bits comprising a broadcast indicator. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein the frame data further comprises: one or more bits indicative of a semiconductor device address, one or more bits indicative of an internal memory address, one or more bits comprising data, and one or more bits comprising a read and write indicator. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the semiconductor device further comprises logic configured to: determine that the one or more broadcast indicator bits are disabled, determine that the read and write indicator bits are indicative of write, match the semiconductor address bits to an address of the semiconductor device, and store the data in the internal memory based on the internal memory address bits. ### Claim 14 (depends on 12) The semiconductor device of claim 12, wherein the semiconductor device further comprises logic configured to: determine that the broadcast indicator bits are enabled, determine that the read and write indicator bits are for write, and store the data in the internal memory based on the internal memory address bits. ### Claim 15 (depends on 12) The semiconductor device of claim 12, wherein the semiconductor device further comprises logic configured to: determine that the read and write indicator bits are for read, match the semiconductor address bits to an address of the semiconductor device, ignore the broadcast indictor bits, and read data from the internal memory based on the internal memory address bits. ### Claim 16 A serial peripheral interface (SPI) system, comprising: a primary SPI chip configured to output frame data and a broadcast indicator signal; and a plurality of secondary SPI chips configured to receive the frame data and the broadcast indicator signal from the primary SPI chip, wherein the secondary SPI chips are further configured to store the frame data in response to the broadcast indicator signal being enabled. ### Claim 17 (depends on 16) The SPI system of claim 16, wherein each of the secondary SPI chips comprises: a first input configured to receive a clock signal; a second input configured to receive the frame data; a third input configured to receive a semiconductor device select signal; one or more fourth inputs configured to receive the broadcast indicator signal; a shift register configured to receive the frame data; and an internal memory to store the frame data. ### Claim 18 (depends on 17) The SPI system of claim 17, wherein, the frame data comprises: one or more bits indicative of a semiconductor device address, one or more bits indicative of an internal memory address, one or more bits comprising data, and one or more bits comprising a read and write indicator. ### Claim 19 (depends on 18) The semiconductor device of claim 18, wherein each of the secondary SPI chips further comprises logic configured to: determine that the broadcast indicator signal is disabled, determine that the read and write indicator bits are for write, match the semiconductor address bits to an address of the semiconductor device, and store the data in the internal memory based on the internal memory address bits. ### Claim 20 (depends on 18) The semiconductor device of claim 18, wherein each of the secondary SPI chips further comprises logic configured to: determine that the broadcast indicator signal is enabled, determine that the read and write indicator bits are for write, and store the data in the internal memory based on the internal memory address bits.