# US 2020/0286554 A1 · Semiconductor device and method for driving the same

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- Number: US 2020/0286554 A1
- Document ID: US20200286554A1
- Status: Published application
- Kind: A1
- Application number: 16/878,757
- Filed: 2020-05-20
- Published: 2020-09-10
- Earliest claimed: 2010-06-25
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Hideki UOCHI; Koichiro KAMATA
- Web page: https://patentgrep.com/patent/US20200286554A1

## CPC

- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C 13/003: {Cell access}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 62/402: {Amorphous materials}
- H10D 62/80: characterised by the materials
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- G11C 2013/0045: {Read using current through the cell}
- G11C 2013/0078: {Write using current through the cell}
- G11C 2213/53: Structure wherein the resistive material being in a transistor, e.g. gate
- H10D 62/875: {being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874)}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.

## Claims

### Claim 1

A memory cell comprising:
a channel formation material;
an insulating material over the channel formation material; and
a charge holding material over the insulating material, the charge holding material comprising gallium, indium, zinc and oxygen.

### Claim 2 (depends on 1)

The memory cell according to claim 1, further comprising:
an electrode overlapping with and being direct contact with the charge holding material.

### Claim 3

A memory cell comprising:
a single crystal substrate having a channel formation region;
an insulating layer over the single crystal substrate;
a charge holding layer over the insulating layer, the charge holding layer comprising gallium, indium, zinc and oxygen; and
an electrode overlapping with and being direct contact with the charge holding layer.

### Claim 4 (depends on 3)

The memory cell according to claim 3, wherein the electrode comprises metal.

### Claim 5 (depends on 3)

The memory cell according to claim 3, wherein the charge holding layer oxide layer is direct contact with the insulating layer.

### Claim 6 (depends on 3)

The memory cell according to claim 3, wherein the electrode is a first electrode, and further comprising a second electrode overlapping with the charge holding layer and the channel formation region of the single crystal substrate.

### Claim 7

A memory cell comprising:
a semiconductor layer comprising a channel formation region;
an insulating layer over the semiconductor layer;
a charge holding layer over the insulating layer, the charge holding layer comprising gallium, indium, zinc and oxygen; and
an electrode overlapping with and being direct contact with the charge holding layer.

### Claim 8 (depends on 7)

The memory cell according to claim 7, wherein the semiconductor layer comprises gallium, indium, zinc and oxygen.

### Claim 9 (depends on 7)

The memory cell according to claim 7, wherein the electrode comprises metal.

### Claim 10 (depends on 7)

The memory cell according to claim 7, wherein the charge holding layer is direct contact with the insulating layer.

### Claim 11 (depends on 7)

The memory cell according to claim 7, wherein the electrode is a first electrode, and further comprising a second electrode overlapping with the charge holding layer and the channel formation region of the semiconductor layer.

### Claim 12

A memory cell comprising:
a single crystal substrate having a channel formation region;
an insulating layer over the single crystal substrate;
a first metal-containing layer over and being direct contact with the insulating layer;
a charge holding layer over and being direct contact with the first metal-containing layer, the charge holding layer comprising gallium, indium, zinc and oxygen; and
an electrode overlapping with the charge holding layer and the channel formation region of the single crystal substrate.

### Claim 13 (depends on 12)

The memory cell according to claim 12, wherein the insulating layer comprises one or more of silicon dioxide, silicon nitride and hafnium oxide.