# US 2020/0286552 A1 · Semiconductor storage device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0286552 A1 - Document ID: US20200286552A1 - Status: Published application - Kind: A1 - Application number: 16/560,584 - Filed: 2019-09-04 - Published: 2020-09-10 - Earliest claimed: 2019-03-06 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Junya MATSUNAMI - Web page: https://patentgrep.com/patent/US20200286552A1 ## CPC - G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell} - G11C 13/003: {Cell access} - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 11/1673: {Reading or sensing circuits or methods} - G11C 11/1693: {Timing circuits or methods} - G11C 11/1677: {Verifying circuits or methods} - G11C 17/146: {Write once memory, i.e. allowing changing of memory content by writing additional bits} - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract According to one embodiment, a semiconductor storage device includes a first wiring, a first resistance change element which is connected to the first wiring, a first nonlinear element which is connected to the first resistance change element, and a second wiring which is connected to the first nonlinear element. In a read operation for the first resistance change element, a voltage between the first wiring and the second wiring increases to a first voltage, and after the voltage between the first wiring and the second wiring increases to the first voltage, the voltage between the first wiring and the second wiring increases to a second voltage which is larger than the first voltage. ## Claims ### Claim 1 A semiconductor storage device, comprising: a first wiring; a first resistance change element connected to the first wiring; a first nonlinear element connected to the first resistance change element; and a second wiring connected to the first nonlinear element, wherein the semiconductor storage device is configured such that in a read operation for the first resistance change element, a voltage applied between the first wiring and the second wiring is increased to a first voltage determined based on a histogram of read threshold voltages of a plurality of memory cells in the semiconductor storage device, and after the voltage applied between the first wiring and the second wiring is increased to the first voltage, the voltage applied between the first wiring and the second wiring is increased to a second voltage which is greater than the first voltage and determined based on the histogram. ### Claim 2 (depends on 1) The semiconductor storage device according to claim 1, further comprising: a third wiring; a second resistance change element connected to the third wiring; a second nonlinear element connected to the second resistance change element; and a fourth wiring connected to the second nonlinear element, wherein the semiconductor storage device is configured such that in a read operation for the second resistance change element, a voltage applied between the third wiring and the fourth wiring is increased to the first voltage, and after the voltage applied between the third wiring and the fourth wiring is increased to the first voltage, the voltage applied between the third wiring and the fourth wiring is maintained at a voltage less than the second voltage. ### Claim 3 A semiconductor storage device, comprising: a first wiring; a first resistance change element connected to the first wiring; a first nonlinear element connected to the first resistance change element; a second wiring connected to the first nonlinear element; and a peripheral circuit connected to the first wiring and the second wiring, wherein in a read operation for the first resistance change element, the peripheral circuit is configured to: increase a voltage between the first wiring and the second wiring until a current flowing through the first resistance change element is greater than a first current, where the voltage is determined according to a histogram of read threshold voltages of a plurality of memory cells in the semiconductor storage device. ### Claim 4 (depends on 3) The semiconductor storage device according to claim 3, wherein the first resistance change element includes a magnetic resistance element. ### Claim 5 (depends on 3) The semiconductor storage device according to claim 3, wherein the first nonlinear element contains a chalcogen. ### Claim 6 (depends on 3) The semiconductor storage device according to claim 3, wherein the first nonlinear element includes a metal layer containing at least one of silver (Ag) and copper (Cu), and an insulating layer. ### Claim 7 (depends on 1) The semiconductor storage device according to claim 1, wherein the voltage applied between the first wiring and the second wiring is increased to the second voltage if a current flowing through the first nonlinear element is less than a current threshold. ### Claim 8 (depends on 7) The semiconductor storage device according to claim 7, wherein the current threshold is predetermined to be larger than the current flowing through the first nonlinear element at the threshold voltage. ### Claim 9 (depends on 2) The semiconductor storage device according to claim 2, wherein each of the first and second resistance change elements includes a magnetic resistance element. ### Claim 10 (depends on 2) The semiconductor storage device according to claim 2, wherein each of the first and second nonlinear elements contains a chalcogen. ### Claim 11 (depends on 2) The semiconductor storage device according to claim 2, wherein each of the first and second nonlinear elements includes a metal layer containing at least one of silver (Ag) and copper (Cu), or an insulating layer. ### Claim 12 (depends on 3) The semiconductor storage device according to claim 3, wherein the peripheral circuit is further configured to: output a first signal if the current flowing through the first resistance change element is greater than the first current and less than a second current, and output a second signal if the current flowing through the first resistance change element is greater than the first current and the second current. ### Claim 13 A method comprising: selecting a first voltage according to a histogram of read threshold voltages of a plurality of memory cells, each memory cell including a resistance change element and nonlinear element coupled to each other; applying the first voltage on one of the plurality of memory cells; comparing a current flowing through the memory cell with a first current threshold; selectively increasing the voltage to the amplitude determined according to the histogram until the current reaches the first current threshold; and outputting a state of data stored in the memory cell based on the comparison of the current with a second current threshold.