# US 2020/0286540 A1 · Dynamic random access memory (dram) cell, dram device and storage method

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- Number: US 2020/0286540 A1
- Document ID: US20200286540A1
- Status: Published application
- Kind: A1
- Application number: 16/883,635
- Filed: 2020-05-26
- Published: 2020-09-10
- Earliest claimed: 2017-12-07
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Kei Kang HUNG; Qi-An XU
- Web page: https://patentgrep.com/patent/US20200286540A1

## CPC

- G11C 11/36: using diodes, e.g. as threshold elements {, i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)}
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C 11/41: forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A DRAM cell includes a transistor, a first diode and a second diode. The transistor has a gate electrically coupled to a word line of an address decoder and a drain electrically coupled to a bit line of the address decoder. The bit line is coupled to a power supply voltage. An anode and a cathode of the first diode are coupled to a cathode and an anode of the second diode, respectively. Each of the first diode and the second diode is coupled at a first end to a source of the transistor at a first node, and at a second end to a node voltage at the second node. A DRAM device includes an address decoder and DRAM cells. A storage method for a DRAM device includes writing data into the DRAM cells and reading data from the DRAM cells.

## Claims

### Claim 1

A dynamic random-access memory (DRAM) cell, comprising:
a transistor having a gate electrically coupled to a word line of an address decoder and a drain electrically coupled to a bit line of the address decoder, wherein the bit line is coupled to a power supply voltage;
a first diode; and
a second diode, wherein an anode of the second diode is coupled to a cathode of the first diode at a first node, and a cathode of the second diode is coupled to an anode of the first diode at a second node, the first node is coupled to a source of the transistor, the second node is coupled to a node voltage,
wherein an absolute value of a difference between the node voltage and the power supply voltage is smaller than a cut-in voltage of the first diode and the second diode.

### Claim 2 (depends on 1)

The DRAM cell of claim 1, further comprising:
a current sense amplifier having a first end coupled to the bit line and a second end coupled to the first node, wherein the current sense amplifier is configured to sense a current between the bit line and the first node, and to amplify and read the current.

### Claim 3 (depends on 1)

The DRAM cell of claim 1, wherein the node voltage equals to a half of the power supply voltage.

### Claim 4 (depends on 1)

The DRAM cell of claim 1, wherein each of the first diode and the second diode comprise a charge-storage diode.

### Claim 5

A dynamic random-access memory (DRAM) device, comprising:
an address decoder, comprising a plurality of word lines and a plurality of bit lines intersecting each other to define a matrix, each of the bit lines configured to write and read data; and
a plurality of DRAM cells distributed in the matrix, each of the DRAM cells coupled to at least one of the bit lines and at least one of the word lines,
wherein the each of the DRAM cells comprises:
a transistor having a gate electrically coupled to a word line of an address decoder and a drain electrically coupled to a bit line of the address decoder, wherein the bit line is coupled to a power supply voltage;
a first diode; and
a second diode, wherein an anode of the second diode is coupled to a cathode of the first diode at a first node, and a cathode of the second diode is coupled to an anode of the first diode at a second node, the first node is coupled to a source of the transistor, the second node is coupled to a node voltage,
wherein an absolute value of a difference between the node voltage and the power supply voltage is smaller than a cut-in voltage of the first diode and the second diode.

### Claim 6 (depends on 5)

The DRAM device of claim 5, wherein the each of the DRAM cell further comprises a current sense amplifier having a first end coupled to the bit line and a second end coupled to the first node, wherein the current sense amplifier is configured to sense a current between the bit line and the first node, and to amplify and read the current.

### Claim 7 (depends on 5)

The DRAM device of claim 5, wherein the node voltage equals to a half of the power supply voltage.

### Claim 8 (depends on 5)

The DRAM device of claim 5, wherein each of the first and second diodes comprises a charge-storage diode.

### Claim 9

A storage method for a dynamic random-access memory (DRAM) device, comprising:
providing a DRAM device comprising an address decoder and a plurality of DRAM cells, the address decoder comprising a plurality of word lines and a plurality of bit lines intersecting each other to define a matrix, each of the bit lines configured to write and read data, the DRAM cells distributed in the matrix, each of the DRAM cells coupled to at least one of the bit lines and at least one of the word lines; and
storing data on the first and second diodes,
wherein the each of the DRAM cells comprises:
a transistor having a gate electrically coupled to a word line of an address decoder and a drain electrically coupled to a bit line of the address decoder, wherein the bit line is coupled to a power supply voltage;
a first diode; and
a second diode, wherein an anode of the second diode is coupled to a cathode of the first diode at a first node, and a cathode of the second diode is coupled to an anode of the first diode at a second node, the first node is coupled to a source of the transistor, the second node is coupled to a node voltage,
wherein an absolute value of a difference between the node voltage and the power supply voltage is smaller than a cut-in voltage of the first diode and the second diode.

### Claim 10 (depends on 9)

The method of claim 9, wherein the each of the DRAM cell further comprises a current sense amplifier having a first end coupled to the bit line and a second end coupled to the first node, wherein the current sense amplifier is configured to sense a current between the bit line and the first node, and to amplify and read the current.

### Claim 11 (depends on 9)

The method of claim 9, wherein each of the first diode and the second diode comprises a charge-storage diode.

### Claim 12 (depends on 9)

The method of claim 9, further comprising:
applying a turn-on voltage to the word line to turn on the transistor and then applying the power supply voltage to the bit line so as to write a datum.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
applying the node voltage to the second node, wherein the node voltage is lower than the power supply voltage; and
after the power supply voltage is introduced into the first diode and the second diode via the transistor and stored therein, removing the turn-on voltage to turn off the transistor.

### Claim 14 (depends on 12)

The method of claim 12, wherein the turn-on voltage is the sum of the power supply voltage and a threshold voltage of the transistor.

### Claim 15 (depends on 12)

The method of claim 12, further comprising:
applying the power supply voltage to the bit line and then applying the turn-on voltage to the word line to turn on the transistor so as to read a datum.

### Claim 16 (depends on 13)

The method of claim 13, further comprising:
sensing an absence or a presence of a current between the bit line and the first node; and
reading the datum stored in the first diode and the second diode based on the absence or presence of the current.

### Claim 17 (depends on 16)

The method of claim 16, wherein a datum of “1” represents the presence of the current between the bit line and the first node.

### Claim 18 (depends on 16)

The method of claim 16, wherein a datum of “0” represents the absence of the current between the bit line and the first node.

### Claim 19 (depends on 9)

The method of claim 9, wherein the power supply voltage includes a high voltage level and a low voltage level.

### Claim 20 (depends on 9)

The method of claim 9, wherein the node voltage applied on the second node equals to a half of the power supply voltage.