Adaptive matrix multiplication accelerator for machine learning and deep learning applications
AssigneeSamsung Electronics Co., Ltd.
InventorsDongyan Jiang, Dimin Niu, Hongzhong Zheng
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Abstract
An adaptive matrix multiplier. In some embodiments, the matrix multiplier includes a first multiplying unit a second multiplying unit, a memory load circuit, and an outer buffer circuit. The first multiplying unit includes a first inner buffer circuit and a second inner buffer circuit, and the second multiplying unit includes a first inner buffer circuit and a second inner buffer circuit. The memory load circuit is configured to load data from memory, in a single burst of a burst memory access mode, into the first inner buffer circuit of the first multiplying unit; and into the first inner buffer circuit of the second multiplying unit.
Claims20
A system, comprising
- a first multiplying unit;
- a second multiplying unit;
- a memory load circuit;
- and
- an outer buffer circuit,
- the first multiplying unit comprising a first inner buffer circuit and a second inner buffer circuit,
- the second multiplying unit comprising a first inner buffer circuit and a second inner buffer circuit,
- the memory load circuit being configured to load data from memory, in a single burst of a burst memory access mode, into:
- the first inner buffer circuit of the first multiplying unit;
- and
- the first inner buffer circuit of the second multiplying unit.
A system, comprising
- a first multiplying unit;
- a second multiplying unit;
- a memory load circuit;
- a memory store circuit;
- and
- an outer buffer circuit,
- the first multiplying unit comprising:
- a multiplying circuit;
- a first inner buffer circuit;
- a second inner buffer circuit;
- a multiplying circuit input multiplexer having a common port connected to an input of the multiplying circuit;
- a multiplying circuit output multiplexer having a common port connected to an output of the multiplying circuit;
- and
- a second inner buffer circuit output multiplexer, having a common port connected to an output of the second inner buffer circuit.
A system, comprising
- a first multiplying unit;
- a second multiplying unit;
- means for loading data from memory;
- and
- an outer buffer circuit,
- the first multiplying unit comprising a first inner buffer circuit and a second inner buffer circuit,
- the second multiplying unit comprising a first inner buffer circuit and a second inner buffer circuit,
- the means for loading data from memory being configured to load data from memory, in a single burst of a burst memory access mode, into:
- the first inner buffer circuit of the first multiplying unit;
- and
- the first inner buffer circuit of the second multiplying unit.
Dependencies are inferred from the claim text.