Coprocessor with Distributed Register

A system comprising:

• a processor configured to issue a first coprocessor instruction to a coprocessor;
• and
• the coprocessor coupled to the processor, wherein the coprocessor comprises:
• a plurality of processing elements arranged in a grid of one or more rows and one or more columns, wherein a given processing element of the plurality of processing elements comprises an arithmetic/logic unit (ALU) circuit configured to execute an operation specified by an instruction issued to the coprocessor;
• and
• a first memory configured to store results generated by the plurality of processing elements, wherein locations in the first memory are specifiable by instructions issued to the coprocessor, and wherein a given location in the first memory is only written by one of the plurality of processing elements, and wherein the first memory is divided into portions and is physically distributed in the plurality of processing elements, wherein the portion distributed to a given processing element of the plurality of processing elements comprises the locations that are writeable by the given processing element.

A method comprising:

• detecting a load instruction that specifies one or more locations in a first memory as a destination for the load instruction, wherein the first memory is physically distributed with a plurality of processing elements that write the first memory with results generated by the plurality of processing elements;
• generating a first operation to load data from a main memory into a temporary location outside of the first memory;
• generating a second operation to move data from the temporary location to the one or more locations in the first memory;
• and
• executing the first operation and the second operation to perform the load instruction.