Technologies for performing column architecture-aware scrambling

A system, comprising:

• a processor;
• and
• a memory comprising a matrix storing individually addressable bit data, the matrix formed by a plurality of rows and a plurality of columns;
• circuitry connected to the memory, wherein the circuitry is to:
• receive a request to perform a write operation of one or more bit values to one of the plurality of columns;
• determine a scrambler state at each location in the one of the plurality of columns, the location corresponding to a respective row and column index of the one of the plurality of columns and the scrambler state being indicative of a pattern used to determine a value at the respective column location;
• scramble each of the bit values as a function of the scrambler state for the respective column location;
• and
• write the scrambled values to each respective column location.

A method comprising:

• receiving, by a device having a memory, a request to perform a read operation to memory, wherein the memory comprises a matrix storing individually addressable bit data, wherein the matrix is formed by a plurality of rows and a plurality of columns, and wherein the read operation specifies to read one or more bit values from one of the plurality of columns;
• determining, by the device, a scrambler state at each location in the one of the plurality of columns, the location corresponding to a respective row and column index of the one of the plurality of columns and the scrambler state being indicative of a pattern used to determine a value at the respective column location;
• descrambling, by the device, each of the bit values as a function of the scrambler state for the respective column location;
• and
• reading, by the device, the descrambled values from each respective column location.

One or more machine-readable storage media storing instructions, which, when executed on a processor, causes a device having a memory to:

• receive a request to perform a read operation to memory, wherein the memory comprises a matrix storing individually addressable bit data, wherein the matrix is formed by a plurality of rows and a plurality of columns, and wherein the read operation specifies to read one or more bit values from one of the plurality of columns;
• determine a scrambler state at each location in the one of the plurality of columns, the location corresponding to a respective row and column index of the one of the plurality of columns and the scrambler state being indicative of a pattern used to determine a value at the respective column location;
• descramble each of the bit values as a function of the scrambler state for the respective column location;
• and
• read the descrambled values from each respective column location.