Display panel circuit structure

Abstract

A display panel circuit structure is provided. The display panel circuit structure includes: a display area and an output bonding area located on a side of the display area. The output bonding area includes: a plurality of first bonding pads arranged in parallel at intervals, and a plurality of first connecting lines between corresponding first bonding pads of the first bonding pads. Each of the first bonding pads includes: a first bottom pad, a first middle pad, and a first top pad. The first bottom pad and the first connecting lines are all located at a first metal layer, the first middle pad is located at a second metal layer, the first top pad is located at a transparent, electrically conductive layer, the first metal layer, the second metal layer, and the transparent, electrically conductive layer are stacked in order, an insulating interlayer is disposed between the first metal layer and the second metal layer, and a passivation layer is disposed between the second metal layer and the transparent, electrically conductive layer. By disposing the first connecting lines at the first metal layer, when a chip is pressed, a problem that any of the first connecting lines between the corresponding first bonding pins of the first bonding pins is short-circuited with any of the corresponding first bonding pins of the first bonding pins is prevented. Therefore, a process yield is improved, and product quality is ensured.

Dependencies are inferred from the claim text.