Memory controller

A memory controller, comprising:

• an error correction encoder configured to perform first error correction encoding operation on messages at a second code rate and generate a plurality of codewords including a target codeword, each codeword including a message part, a first parity part, and a second parity part, the error correction encoder further configured to perform second error correction encoding on second parity parts of the plurality of codewords and generate a parity codeword corresponding to the plurality of codewords;
• and
• an error correction decoder in communication with the error correction encoder and configured to perform at least one of first error correction decoding at a first code rate greater than the second code rate or second error correction decoding at the second code rate, wherein the first error correction decoding is performed based on a first parity check matrix and log likelihood ratio (UR) values corresponding to a partial codeword of the target codeword, the partial codeword including the message part and the first parity part, and wherein the second error correction decoding is performed based on a second parity check matrix and LLR values corresponding to an entire target codeword.