Shift Register and Driving Method Thereof, Cascade Driving Circuit and Display Device

A driving method of a shift register,

• the shift register comprising:
• a precharge circuit coupled to a precharge signal input terminal, a first clock signal terminal and a first pull-up node;
• a first node control circuit coupled to a first power supply terminal, a second power supply terminal, a third clock signal terminal, the first pull-up node and a first pull-down node;
• a first output circuit coupled to a first signal output terminal, the second power supply terminal, a second clock signal terminal, the first pull-up node and the first pull-down node;
• a second node control circuit coupled to the precharge signal input terminal, the first power supply terminal, the second power supply terminal, the first clock signal terminal, the third clock signal terminal, a second pull-up node, and a second pull-down node;
• and
• a second output circuit coupled to the first power supply terminal, the second power supply terminal, the first pull-up node and the first pull-down node, the driving method comprising:
• in a precharge phase, writing a precharge signal provided through the precharge signal input terminal to the first pull-up node by the precharge circuit, writing a second operating voltage provided through the second power supply terminal to the first pull-up node by the first node control circuit, writing the precharge signal to the second pull-down node and writing the second operating voltage to the second pull-up node by the second node control circuit, writing a second clock signal provided through the second clock signal terminal to the first signal output terminal by the first output circuit, and writing the second operating voltage to the second signal output terminal by the second output circuit;
• in an output phase, continuously writing the second clock signal to the first signal output terminal by the first output circuit, and continuously writing the second operating voltage to the second signal output terminal by the second output circuit;
• and
• in a reset phase, writing a first operating voltage provided through the first power supply terminal to the first pull-down node and the second operating voltage to the first pull-up node by the first node control circuit, writing the second operating voltage to the second pull-down node and the first operating voltage to the second pull-up node by the second node control circuit, writing the second operating voltage to the first signal output terminal by the first output circuit, and writing the first operating voltage to the second signal output terminal by the second output circuit.