US 2020/0266803 A1 · LATCHED COMPARATOR, CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS RELATING TO THE LATCHED COMPARATOR

Abstract

A latched comparator includes a first amplification circuit, a second amplification circuit and a latch circuit. The first amplification circuit changes voltage levels of first and second output nodes based on first and second input signals when an operation speed of a semiconductor apparatus is relatively slow. The second amplification circuit changes voltage levels of third and fourth output nodes based on the first and second input signals when the operation speed of the semiconductor apparatus is relatively fast. The latch circuit generates first and second latch signals based on the voltage levels of the first and second output nodes or based on the voltage levels of the third and fourth output nodes according to the operation speed of the semiconductor apparatus.

Claims29

Dependent claims

A latched comparator comprising:

a first amplification circuit configured to change one between voltage levels of a first output node and a second output node to a first voltage level by amplifying a first input signal and a second input signal based on a frequency detection signal;
a second amplification circuit configured to change one between voltage levels of a third output node and a fourth output node to a second voltage level by amplifying the first input signal and the second input signal based on the frequency detection signal, the second voltage level being lower than the first voltage level;
and
a latch circuit configured to generate a first latch signal and a second latch signal based on the voltage levels of the first output node and the second output node or generate the first latch signal and the second latch signal based on the voltage levels of the third output node and the fourth output node, based on the frequency detection signal.

1 more element

A latched comparator comprising:

an amplification circuit configured to change one between voltage levels of a first output node and a second output node to a first voltage level based on a first input signal and a second input signal when voltage levels of the first input signal and the second input signal are within a first range, and change one between voltage levels of a third output node and a fourth output node to a second voltage level based on the first input signal and the second input signal when the voltage levels of the first input signal and the second input signal are within a second range higher than the first range, the second voltage level being lower than the first voltage level;
and
a latch circuit configured to generate a first latch signal and a second latch signal based on the voltage levels of the first output node and the second output node when the voltage levels of the first input signal and the second input signal are within the first range, and generate the first latch signal and the second latch signal based on the voltage levels of the third output node and the fourth output node when the voltage levels of the first input signal and the second input signal are within the second range.

A semiconductor apparatus comprising:

a frequency detector configured to generate a frequency detection signal by detecting a frequency of a clock signal;
a duty detector configured to generate a first detection signal and a second detection signal having voltage levels within one between a first range and a second range based on at least two internal clock signals;
a first amplification circuit configured to change voltage levels of a first output node and a second output node by amplifying the first detection signal and the second detection signal having the voltage levels within the first range based on the frequency detection signal;
a second amplification circuit configured to change voltage levels of a third output node and a fourth output node by amplifying the first detection signal and the second detection signal having the voltage levels within the second range based on the frequency detection signal;
and
a latch circuit configured to generate a first latch signal and a second latch signal based on the voltage levels of the first output node and the second output node or generate the first latch signal and the second latch signal based on the voltage levels of the third output node and the fourth output node, based on the frequency detection signal.

3 more elements

Dependencies are inferred from the claim text.

Latched comparator, clock generation circuit and semiconductor apparatus relating to the latched comparator

Life of this patent

Latched comparator, clock generation circuit and semiconductor apparatus relating to the latched comparator

Life of this patent

Abstract

Claims29