Power-on reset circuit

A circuit comprising:

• a voltage source terminal;
• a resistor;
• a first transistor having a first control terminal and first and second voltage terminals, the first voltage terminal coupled to the voltage source terminal, and the first control terminal coupled through the resistor to the second voltage terminal;
• a second transistor having a second control terminal and third and fourth voltage terminals, the third voltage terminal coupled through the resistor to the second voltage terminal, and the second control terminal coupled to the third voltage terminal;
• an offset circuit including third and fourth transistors, in which the third transistor is cascoded to the fourth transistor, and a threshold voltage of the third transistor is greater than a threshold voltage of the fourth transistor;
• and
• a comparator having first and second comparator inputs, the first comparator input coupled to the second voltage terminal, and the second comparator input coupled through the offset circuit to the voltage source terminal.

A system, comprising:

• a voltage source terminal;
• and
• a power-on reset (POR) circuit including:
• a resistor;
• a first transistor having first and second terminals, the first terminal coupled to the voltage source terminal, the second terminal coupled to the resistor, and the first transistor configured to:
• operate in a sub-threshold region of the first transistor;
• generate a sub-threshold current through the resistor;
• and output a reference voltage at the second terminal based on the sub-threshold current;
• a second transistor coupled through the resistor to the second terminal and configured to receive the sub-threshold current;
• a comparator having a comparator output and first and second comparator inputs, the first comparator input coupled to the second terminal, and the comparator configured to generate a power-on reset signal at the comparator output based on a comparison between the reference voltage at the first comparator input and an offset voltage at the second comparator input;
• and
• an offset circuit coupled between the voltage source terminal and the second comparator input, in which the offset circuit is configured to generate the offset voltage at the second comparator input, the offset circuit includes third and fourth transistors, the third transistor is cascoded to the fourth transistor, and a threshold voltage of the third transistor is greater than a threshold voltage of the fourth transistor.

A circuit comprising:

• a voltage source terminal;
• a reference circuit coupled to the voltage source terminal, the reference circuit including a resistor and first and second transistors, in which the first transistor has an output terminal coupled through the resistor to the second transistor, and the first transistor is configured to operate in a sub-threshold region and generate a reference voltage at the output terminal;
• a comparator having a comparator output and first and second comparator inputs, the first comparator input coupled to the output terminal, and the comparator configured to:
• compare the reference voltage at the first comparator input and a voltage at the second comparator input;
• and generate an output signal at the comparator output based on the comparison;
• and
• an offset circuit coupled between the voltage source terminal and the second comparator input, in which the offset circuit is configured to generate the voltage at the second comparator input, the offset circuit includes third and fourth transistors, the third transistor is cascoded to the fourth transistor, and a threshold voltage of the third transistor is greater than a threshold voltage of the fourth transistor.