Magnetoresistive Random Access Memory Cell and Fabricating the Same

A method comprising:

• providing a film stack over a substrate, the film stack including a free layer, a barrier disposed over the free layer, a pin layer disposed over the barrier layer and anti-ferromagnetic layer disposed over the pin layer;
• forming a first top electrode layer directly on the anti-ferromagnetic layer;
• performing a first patterning process to pattern the first top electrode layer, the anti-ferromagnetic layer, and the pin layer, wherein a top surface of the barrier layer is exposed after the performing of the first patterning process;
• forming a first capping layer along sidewalls of the patterned first top electrode layer, the patterned anti-ferromagnetic layer, and the patterned pin layer;
• performing a second patterning process to pattern the barrier layer and the free layer while using the first capping layer, the patterned first top electrode layer, the patterned anti-ferromagnetic layer, and the patterned pin layer as a mask;
• forming a second capping layer on the first capping layer and sidewalls of the patterned barrier layer and the patterned free layer;
• and
• removing a portion of the second capping layer to expose a portion of the patterned first top electrode layer.

A method comprising:

• forming a first electrode layer on a substrate;
• providing a film stack directly on the first electrode layer, the film stack including a free layer, a barrier disposed over the free layer, a pin layer disposed over the barrier layer and anti-ferromagnetic layer disposed over the pin layer;
• forming a second electrode layer on the anti-ferromagnetic layer;
• forming a patterned hard mask on the second electrode layer;
• patterning the second electrode layer, the anti-ferromagnetic layer, and the pin layer using the patterned hard mask as a mask;
• forming a first capping layer directly on sidewalls the patterned hard mask, the patterned second electrode layer, the patterned anti-ferromagnetic layer, and the patterned pin layer;
• patterning the barrier layer and the free layer while using the patterned hard mask and the first capping layer as a mask;
• forming a second capping layer directly on the first capping layer and sidewalls of the patterned barrier layer and the patterned free layer;
• forming a dielectric layer on the second capping layer, and
• removing a portion of the second capping layer to expose a portion of the patterned second electrode layer.