Resistive random access memory circuit
AssigneeWinbond Electronics Corp.
InventorsChia-Ming LIU, Ting-Ying SHEN, Ming-Che LIN
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Abstract
An RRAM circuit includes a first RRAM cell, a second RRAM cell, a first transistor, and a second transistor. The first RRAM cell is coupled between a first bit line and a first node. The second RRAM cell is coupled between a second bit line and the first node. The first transistor includes a first gate terminal, a first drain terminal, and a first source terminal. The first gate terminal is coupled to a first word line, the first drain terminal is coupled to the first node, and the first source terminal is coupled to a first source line. The second gate terminal is coupled to the first word line, the second drain terminal is coupled to the first node, and the second source terminal is coupled to a second source line.
Claims10
A RRAM circuit, comprising:
- a first RRAM cell, coupled between a first bit line and a first node;
- a second RRAM cell, coupled between a second bit line and the first node;
- a first transistor, comprising a first gate terminal, a first drain terminal, and a first source terminal, wherein the first gate terminal is coupled to a first word line, the first drain terminal is coupled to the first node, and the first source terminal is coupled to a first source line;
- and
- a second transistor, comprising a second gate terminal, a second drain terminal, and a second source terminal, wherein the second gate terminal is coupled to the first word line, the second drain terminal is coupled to the first node, and the second source terminal is coupled to a second source line.
Dependencies are inferred from the claim text.