Method of fabricating integrated circuit

A method of fabricating an integrated circuit comprising a resistive random-access memory cell and a resistor cell, comprising:

• providing a substrate having a resistive random-access memory area and a resistor area;
• depositing a first dielectric layer on the substrate blanketly;
• depositing and etching a bottom conductive layer, an insulating layer and a top conductive layer to form a patterned stacked structure in the resistive random-access memory area and the resistor area;
• depositing a second dielectric layer on the patterned stacked structure;
• and
• forming a first metal plug, a second metal plug, a third metal plug and a fourth metal plug in the second dielectric layer simultaneously, wherein the first metal plug and the second metal plug contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby the patterned stacked structure in the resistive random-access memory area constituting the resistive random-access memory cell, and the third metal plug and the fourth metal plug contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby the patterned stacked structure in the resistor area constituting the resistor cell.