Channel hole and bitline architecture and method to improve page or block size and performance of 3d nand

A method for forming a memory finger in a three-dimensional memory device, comprising:

• forming, on a first substrate, an alternating layer stack;
• forming a plurality of slit structures each extending vertically through the alternating layer stack and laterally along a wordline direction to divide the alternating layer stack into at least one memory finger;
• forming, in the alternating layer stack, a plurality of conductor/dielectric layer pairs;
• forming a first column of vertical memory strings extending through the alternating layer stack in the at least one memory finger, wherein the vertical memory strings in the first column are displaced relative to each other along the wordline direction;
• forming a second column of vertical memory strings extending through the alternating layer stack in the at least one memory finger, wherein the vertical memory strings in the second column are displaced relative to each other along the wordline direction;
• and
• forming a plurality of bitlines displaced along the wordline direction and extending along a bitline direction in the at least one memory finger, wherein each bitline is connected to an individual vertical memory string in the first and second columns.