Three-dimensional memory device including bit lines between memory elements and an underlying peripheral circuit and methods of making the same

A method of forming a three-dimensional memory device, comprising:

• forming field effect transistors on or over a top surface of the substrate;
• forming bit lines within a lower-interconnect-level dielectric material layers over the field effect transistors, wherein the bit lines are laterally spaced apart along a first horizontal direction, and laterally extend a long a second horizontal direction that is perpendicular to the first horizontal direction;
• forming bit-line-connection via structures within a via-level dielectric layer on a top surface of a respective one of the bit lines;
• forming pillar-shaped drain regions on a respective one of the bit-line-connection via structures;
• forming an alternating stack of insulating layers and spacer material layers over the pillar-shaped drain regions, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;
• forming memory openings through the alternating stack on a respective one of the pillar-shaped drain regions;
• forming memory opening fill structures including a respective memory stack structure that contains a respective vertical semiconductor channel and a respective vertical stack of memory elements in the memory openings;
• and
• forming a source layer over the alternating stack, wherein the source layer is electrically connected to an upper end of each vertical semiconductor channel within a subset of the vertical semiconductor channels.